diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/cpu/inorder/inorder_dyn_inst.cc | 14 | ||||
-rw-r--r-- | src/cpu/inorder/inorder_dyn_inst.hh | 3 | ||||
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 7 | ||||
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.hh | 11 | ||||
-rw-r--r-- | src/cpu/inorder/resources/tlb_unit.hh | 17 |
5 files changed, 36 insertions, 16 deletions
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc index 9355a9f6f..da73d482a 100644 --- a/src/cpu/inorder/inorder_dyn_inst.cc +++ b/src/cpu/inorder/inorder_dyn_inst.cc @@ -108,7 +108,9 @@ InOrderDynInst::setMachInst(ExtMachInst machInst) void InOrderDynInst::initVars() { - req = NULL; + fetchMemReq = NULL; + dataMemReq = NULL; + effAddr = 0; physEffAddr = 0; @@ -170,8 +172,14 @@ InOrderDynInst::initVars() InOrderDynInst::~InOrderDynInst() { - if (req) { - delete req; + if (fetchMemReq != 0x0) { + delete fetchMemReq; + fetchMemReq = NULL; + } + + if (dataMemReq != 0x0) { + delete dataMemReq; + dataMemReq = NULL; } if (traceData) { diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh index 042a6485a..86c60221e 100644 --- a/src/cpu/inorder/inorder_dyn_inst.hh +++ b/src/cpu/inorder/inorder_dyn_inst.hh @@ -634,7 +634,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted /** Read Effective Address from instruction & do memory access */ Fault memAccess(); - RequestPtr memReq; + RequestPtr fetchMemReq; + RequestPtr dataMemReq; bool memAddrReady; diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 5e374fa40..68daee512 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -252,6 +252,8 @@ CacheUnit::execute(int slot_num) break; case CompleteFetch: + // @TODO: MOVE Functionality of handling fetched data into 'fetch unit' + // let cache-unit just be responsible for transferring data. if (cache_req->isMemAccComplete()) { DPRINTF(InOrderCachePort, "[tid:%i]: Completing Fetch Access for [sn:%i]\n", @@ -284,6 +286,8 @@ CacheUnit::execute(int slot_num) inst->traceData->setPC(inst->readPC()); } + delete cache_req->dataPkt; + cache_req->done(); } else { DPRINTF(InOrderCachePort, @@ -481,6 +485,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt) cache_pkt->cacheReq->getInst()->seqNum); cache_pkt->cacheReq->done(); + delete cache_pkt; return; } @@ -543,6 +548,8 @@ CacheUnit::processCacheCompletion(PacketPtr pkt) getMemData(cache_pkt)); } + + delete cache_pkt; } cache_req->setMemAccPending(false); diff --git a/src/cpu/inorder/resources/cache_unit.hh b/src/cpu/inorder/resources/cache_unit.hh index 219329683..4cde686b8 100644 --- a/src/cpu/inorder/resources/cache_unit.hh +++ b/src/cpu/inorder/resources/cache_unit.hh @@ -246,7 +246,13 @@ class CacheRequest : public ResourceRequest : ResourceRequest(cres, inst, stage_num, res_idx, slot_num, cmd), pktCmd(pkt_cmd), memAccComplete(false), memAccPending(false) { - memReq = inst->memReq; + if (cmd == CacheUnit::InitiateFetch || + cmd == CacheUnit::CompleteFetch || + cmd == CacheUnit::Fetch) { + memReq = inst->fetchMemReq; + } else { + memReq = inst->dataMemReq; + } reqData = new uint8_t[req_size]; retryPkt = NULL; @@ -273,9 +279,6 @@ class CacheRequest : public ResourceRequest delete retryPkt; } #endif - - if (memReq) - delete memReq; } virtual PacketDataPtr getData() diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh index 67e1bda1d..4ca240ba8 100644 --- a/src/cpu/inorder/resources/tlb_unit.hh +++ b/src/cpu/inorder/resources/tlb_unit.hh @@ -106,21 +106,22 @@ class TLBUnitRequest : public ResourceRequest { aligned_addr = inst->getMemAddr(); req_size = sizeof(TheISA::MachInst); flags = 0; + inst->fetchMemReq = new Request(inst->readTid(), aligned_addr, req_size, + flags, inst->readPC(), res->cpu->readCpuId(), inst->readTid()); + memReq = inst->fetchMemReq; } else { aligned_addr = inst->getMemAddr();; req_size = inst->getMemAccSize(); flags = inst->getMemFlags(); - } - if (req_size == 0 && (inst->isDataPrefetch() || inst->isInstPrefetch())) { - req_size = 8; - } + if (req_size == 0 && (inst->isDataPrefetch() || inst->isInstPrefetch())) { + req_size = 8; + } - // @TODO: Add Vaddr & Paddr functions - inst->memReq = new Request(inst->readTid(), aligned_addr, req_size, + inst->dataMemReq = new Request(inst->readTid(), aligned_addr, req_size, flags, inst->readPC(), res->cpu->readCpuId(), inst->readTid()); - - memReq = inst->memReq; + memReq = inst->dataMemReq; + } } RequestPtr memReq; |