diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/inorder/SConscript | 2 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 66 |
2 files changed, 37 insertions, 31 deletions
diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript index aa579a179..94fb5ae7f 100644 --- a/src/cpu/inorder/SConscript +++ b/src/cpu/inorder/SConscript @@ -61,7 +61,7 @@ if 'InOrderCPU' in env['CPU_MODELS']: 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred', 'InOrderDecode', 'InOrderExecute', 'InOrderInstBuffer', 'InOrderUseDef', 'InOrderGraduation', 'InOrderCachePort', 'RegDepMap', 'Resource', - 'ThreadModel', 'AddrDep']) + 'InOrderStall','ThreadModel', 'AddrDep']) Source('inorder_dyn_inst.cc') Source('inorder_cpu_builder.cc') diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index ee7ec8212..0673d6b9b 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -338,7 +338,7 @@ CacheUnit::requestAgain(DynInstPtr inst, bool &service_request) cache_req->cmd = inst->curSkedEntry->cmd; DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: Updating the command for this " - "instruction\n ", inst->readTid(), inst->seqNum); + "instruction\n", inst->readTid(), inst->seqNum); service_request = true; } else if (inst->curSkedEntry->idx != CacheUnit::InitSecondSplitRead && @@ -725,40 +725,46 @@ CacheUnit::execute(int slot_num) break; case CompleteWriteData: - DPRINTF(InOrderCachePort, - "[tid:%i]: [sn:%i]: Trying to Complete Data Write Access\n", - tid, inst->seqNum); - DPRINTF(InOrderCachePort, - "[tid:%i]: [sn:%i]: cSwap:%i LLSC:%i isSwap:%i isCond:%i\n", - tid, inst->seqNum, - cache_req->memReq->isCondSwap(), - cache_req->memReq->isLLSC(), - cache_req->memReq->isSwap(), - inst->isStoreConditional()); + { + DPRINTF(InOrderCachePort, + "[tid:%i]: [sn:%i]: Trying to Complete Data Write Access\n", + tid, inst->seqNum); - //@todo: check that timing translation is finished here - if (cache_req->dataPkt->isRead()) { - assert(cache_req->memReq->isCondSwap() || - cache_req->memReq->isLLSC() || - cache_req->memReq->isSwap()); - - if (!cache_req->isMemAccComplete()) { - DPRINTF(InOrderStall, "STALL: [tid:%i]: Data miss from %08p\n", - tid, cache_req->inst->getMemAddr()); - cache_req->setCompleted(false); - cache_req->setMemStall(true); - return; + //@todo: check that timing translation is finished here + RequestPtr mem_req = cache_req->memReq; + DPRINTF(InOrderCachePort, + "[tid:%i]: [sn:%i]: cSwap:%i LLSC:%i isSwap:%i isCond:%i\n", + tid, inst->seqNum, + mem_req->isCondSwap(), + mem_req->isLLSC(), + mem_req->isSwap(), + inst->isStoreConditional()); + + if (mem_req->isCondSwap() || mem_req->isLLSC() || mem_req->isSwap()) { + DPRINTF(InOrderCachePort, "Detected Conditional Store Inst.\n"); + + if (!cache_req->isMemAccComplete()) { + DPRINTF(InOrderStall, "STALL: [tid:%i]: Data miss from %08p\n", + tid, cache_req->inst->getMemAddr()); + cache_req->setCompleted(false); + cache_req->setMemStall(true); + return; + } else { + DPRINTF(InOrderStall, "Mem Acc Completed\n"); + } } - } - if (cache_req->isMemAccPending()) { - cache_req->dataPkt->reqData = cache_req->reqData; - cache_req->dataPkt->memReq = cache_req->memReq; - } + if (cache_req->isMemAccPending()) { + DPRINTF(InOrderCachePort, "Store Instruction Pending Completion.\n"); + cache_req->dataPkt->reqData = cache_req->reqData; + cache_req->dataPkt->memReq = cache_req->memReq; + } else + DPRINTF(InOrderCachePort, "Store Instruction Finished Completion.\n"); - //@todo: if split inst save data + //@todo: if split inst save data - finishCacheUnitReq(inst, cache_req); + finishCacheUnitReq(inst, cache_req); + } break; case CompleteSecondSplitRead: |