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-rw-r--r--src/cpu/simple/atomic.cc8
-rw-r--r--src/cpu/simple/timing.cc8
2 files changed, 0 insertions, 16 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 7740434d8..d96adffd5 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -351,10 +351,6 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
}
}
- // This will need a new way to tell if it has a dcache attached.
- if (req->isUncacheable())
- recordEvent("Uncached Read");
-
//If there's a fault, return it
if (fault != NoFault) {
if (req->isPrefetch()) {
@@ -523,10 +519,6 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
}
}
- // This will need a new way to tell if it's hooked up to a cache or not.
- if (req->isUncacheable())
- recordEvent("Uncached Write");
-
//If there's a fault or we don't need to access a second cache line,
//stop now.
if (fault != NoFault || secondAddr <= addr)
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 7583c09e6..b8fc5ab84 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -436,10 +436,6 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
Addr split_addr = roundDown(addr + data_size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
- // This will need a new way to tell if it's hooked up to a cache or not.
- if (req->isUncacheable())
- recordEvent("Uncached Write");
-
_status = DTBWaitResponse;
if (split_addr > addr) {
RequestPtr req1, req2;
@@ -558,10 +554,6 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
Addr split_addr = roundDown(addr + data_size - 1, block_size);
assert(split_addr <= addr || split_addr - addr < block_size);
- // This will need a new way to tell if it's hooked up to a cache or not.
- if (req->isUncacheable())
- recordEvent("Uncached Write");
-
T *dataP = new T;
*dataP = TheISA::htog(data);
_status = DTBWaitResponse;