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-rw-r--r--src/arch/sparc/isa/formats/mem/swap.isa10
-rw-r--r--src/cpu/base_dyn_inst.hh5
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh5
-rw-r--r--src/cpu/o3/regfile.hh14
-rw-r--r--src/cpu/o3/rename_impl.hh10
5 files changed, 30 insertions, 14 deletions
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index 818597a84..b71542a2b 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -137,7 +137,7 @@ def format Swap(code, postacc_code, mem_flags, *opt_flags) {{
decoder_output,
exec_output,
decode_block) = doMemFormat(code, SwapFuncs, '', name, Name, flags,
- opt_flags, postacc_code)
+ ["IsStoreConditional"], postacc_code)
}};
def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
@@ -148,7 +148,7 @@ def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
decoder_output,
exec_output,
decode_block) = doMemFormat(code, SwapFuncs, AlternateASIPrivFaultCheck,
- name, Name, flags, opt_flags, postacc_code)
+ name, Name, flags, ["IsStoreConditional"], postacc_code)
}};
@@ -163,8 +163,8 @@ let {{
decode_block = BasicDecode.subst(iop)
microParams = {"code": code, "postacc_code" : postacc_code,
"ea_code" : addrCalcReg, "fault_check" : faultCode}
- exec_output = doSplitExecute(execute, name, Name, asi, opt_flags,
- microParams);
+ exec_output = doSplitExecute(execute, name, Name, asi,
+ ["IsStoreConditional"], microParams);
return (header_output, decoder_output, exec_output, decode_block)
}};
@@ -177,7 +177,7 @@ def format CasAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
decoder_output,
exec_output,
decode_block) = doCasFormat(code, SwapFuncs, AlternateASIPrivFaultCheck,
- name, Name, flags, opt_flags, postacc_code)
+ name, Name, flags, ["IsStoreConditional"], postacc_code)
}};
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 6c6d90076..eed05c2f1 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -877,6 +877,11 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
effAddrValid = true;
physEffAddr = req->getPaddr();
memReqFlags = req->getFlags();
+
+ if (req->isCondSwap()) {
+ assert(res);
+ req->setExtraData(*res);
+ }
#if 0
if (cpu->system->memctrl->badaddr(physEffAddr)) {
fault = TheISA::genMachineCheckFault();
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index d558e2dfa..44e2cea76 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -647,7 +647,8 @@ LSQUnit<Impl>::writebackStores()
memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
- PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq,
+ MemCmd command = req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq;
+ PacketPtr data_pkt = new Packet(req, command,
Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
@@ -664,7 +665,7 @@ LSQUnit<Impl>::writebackStores()
inst->seqNum);
// @todo: Remove this SC hack once the memory system handles it.
- if (req->isLocked()) {
+ if (inst->isStoreConditional()) {
// Disable recording the result temporarily. Writing to
// misc regs normally updates the result, but this is not
// the desired behavior when handling store conditionals.
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index bbc69fc96..b5b1cd021 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -174,7 +174,7 @@ class PhysRegFile
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
- assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
+ assert(reg_idx < numPhysicalFloatRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
@@ -189,7 +189,7 @@ class PhysRegFile
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
- assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
+ assert(reg_idx < numPhysicalFloatRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
@@ -204,7 +204,7 @@ class PhysRegFile
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
- assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
+ assert(reg_idx < numPhysicalFloatRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
@@ -217,7 +217,7 @@ class PhysRegFile
// Remove the base Float reg dependency.
reg_idx = reg_idx - numPhysicalIntRegs;
- assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs);
+ assert(reg_idx < numPhysicalFloatRegs);
DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
int(reg_idx), (uint64_t)val);
@@ -232,11 +232,11 @@ class PhysRegFile
MiscReg readMiscReg(int misc_reg, unsigned thread_id)
{
- return miscRegs[thread_id].readReg(misc_reg,
- cpu->tcBase(thread_id));
+ return miscRegs[thread_id].readReg(misc_reg, cpu->tcBase(thread_id));
}
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned thread_id)
+ void setMiscRegNoEffect(int misc_reg,
+ const MiscReg &val, unsigned thread_id)
{
miscRegs[thread_id].setRegNoEffect(misc_reg, val);
}
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index c0d34116d..6b7fb1e08 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -996,7 +996,12 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid)
if (src_reg < TheISA::FP_Base_DepTag) {
flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
+ } else {
+ // Floating point and Miscellaneous registers need their indexes
+ // adjusted to account for the expanded number of flattened int regs.
+ flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
}
+
inst->flattenSrcReg(src_idx, flat_src_reg);
// Look up the source registers to get the phys. register they've
@@ -1033,8 +1038,13 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst,unsigned tid)
RegIndex dest_reg = inst->destRegIdx(dest_idx);
RegIndex flat_dest_reg = dest_reg;
if (dest_reg < TheISA::FP_Base_DepTag) {
+ // Integer registers are flattened.
flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
+ } else {
+ // Floating point and Miscellaneous registers need their indexes
+ // adjusted to account for the expanded number of flattened int regs.
+ flat_dest_reg = dest_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
}
inst->flattenDestReg(dest_idx, flat_dest_reg);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 07:12:23 +0000