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-rw-r--r--src/arch/arm/locked_mem.hh7
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh3
-rw-r--r--src/mem/cache/blk.hh2
-rw-r--r--src/mem/cache/mshr.hh6
4 files changed, 16 insertions, 2 deletions
diff --git a/src/arch/arm/locked_mem.hh b/src/arch/arm/locked_mem.hh
index f324f773b..8aa181245 100644
--- a/src/arch/arm/locked_mem.hh
+++ b/src/arch/arm/locked_mem.hh
@@ -64,7 +64,10 @@ template <class XC>
inline void
handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
{
- DPRINTF(LLSC,"%s: handleing snoop for address: %#x locked: %d\n",
+ // Should only every see invalidations / direct writes
+ assert(pkt->isInvalidate() || pkt->isWrite());
+
+ DPRINTF(LLSC,"%s: handling snoop for address: %#x locked: %d\n",
xc->getCpuPtr()->name(),pkt->getAddr(),
xc->readMiscReg(MISCREG_LOCKFLAG));
if (!xc->readMiscReg(MISCREG_LOCKFLAG))
@@ -74,7 +77,7 @@ handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
// If no caches are attached, the snoop address always needs to be masked
Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
- DPRINTF(LLSC,"%s: handleing snoop for address: %#x locked addr: %#x\n",
+ DPRINTF(LLSC,"%s: handling snoop for address: %#x locked addr: %#x\n",
xc->getCpuPtr()->name(),snoop_addr, locked_addr);
if (locked_addr == snoop_addr) {
DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n",
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index b87ab0240..73be5e56f 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -435,6 +435,9 @@ template <class Impl>
void
LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
{
+ // Should only ever get invalidations in here
+ assert(pkt->isInvalidate());
+
int load_idx = loadHead;
DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr());
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 39d45d6e1..700847030 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -335,6 +335,8 @@ class CacheBlk
*/
bool checkWrite(PacketPtr pkt)
{
+ assert(pkt->isWrite());
+
// common case
if (!pkt->isLLSC() && lockList.empty())
return true;
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 82a674672..ea3719343 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -149,7 +149,13 @@ class MSHR : public Packet::SenderState, public Printable
bool isReset() const { return !needsWritable && !hasUpgrade; }
void add(PacketPtr pkt, Tick readyTime, Counter order,
Target::Source source, bool markPending);
+
+ /**
+ * Convert upgrades to the equivalent request if the cache line they
+ * refer to would have been invalid (Upgrade -> ReadEx, SC* -> Fail).
+ * Used to rejig ordering between targets waiting on an MSHR. */
void replaceUpgrades();
+
void clearDownstreamPending();
bool checkFunctional(PacketPtr pkt);
void print(std::ostream &os, int verbosity,