diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/input_output/general_io.py | 8 | ||||
| -rw-r--r-- | src/arch/x86/isa/insts/general_purpose/input_output/string_io.py | 8 | ||||
| -rw-r--r-- | src/cpu/o3/iew_impl.hh | 6 | ||||
| -rw-r--r-- | src/cpu/pc_event.cc | 6 | ||||
| -rw-r--r-- | src/dev/io_device.cc | 2 | ||||
| -rw-r--r-- | src/python/m5/SimObject.py | 10 |
6 files changed, 33 insertions, 7 deletions
diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py index c034f8a48..0465b3447 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py @@ -42,26 +42,34 @@ microcode = ''' def macroop IN_R_I { .adjust_imm trimImm(8) limm t1, imm, dataSize=asz + mfence ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence }; def macroop IN_R_R { zexti t2, regm, 15, dataSize=8 + mfence ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence }; def macroop OUT_I_R { .adjust_imm trimImm(8) limm t1, imm, dataSize=8 + mfence st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence }; def macroop OUT_R_R { zexti t2, reg, 15, dataSize=8 + mfence st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence }; ''' diff --git a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py index 3c90ee7e7..044e57edc 100644 --- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py +++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py @@ -45,9 +45,11 @@ def macroop INS_M_R { zexti t2, reg, 15, dataSize=8 + mfence ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True st t6, es, [1, t0, rdi] + mfence add rdi, rdi, t3, dataSize=asz }; @@ -63,6 +65,7 @@ def macroop INS_E_M_R { zexti t2, reg, 15, dataSize=8 + mfence topOfLoop: ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True @@ -72,6 +75,7 @@ topOfLoop: add rdi, rdi, t3, dataSize=asz br label("topOfLoop"), flags=(nCEZF,) end: + mfence fault "NoFault" }; @@ -84,9 +88,11 @@ def macroop OUTS_R_M { zexti t2, reg, 15, dataSize=8 + mfence ld t6, ds, [1, t0, rsi] st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ nonSpec=True + mfence add rsi, rsi, t3, dataSize=asz }; @@ -102,6 +108,7 @@ def macroop OUTS_E_R_M { zexti t2, reg, 15, dataSize=8 + mfence topOfLoop: ld t6, ds, [1, t0, rsi] st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \ @@ -111,6 +118,7 @@ topOfLoop: add rsi, rsi, t3, dataSize=asz br label("topOfLoop"), flags=(nCEZF,) end: + mfence fault "NoFault" }; ''' diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 9c4b1068d..92c8875e4 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -1340,10 +1340,10 @@ DefaultIEW<Impl>::executeInsts() fetchRedirect[tid] = true; DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); - DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", - inst->predInstAddr(), inst->predNextInstAddr()); + DPRINTF(IEW, "Predicted target was PC: %s.\n", + inst->readPredTarg()); DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", - inst->pcState(), inst->nextInstAddr()); + inst->pcState()); // If incorrect, then signal the ROB that it must be squashed. squashDueToBranch(inst, tid); diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc index f9955d014..385a83b27 100644 --- a/src/cpu/pc_event.cc +++ b/src/cpu/pc_event.cc @@ -84,7 +84,9 @@ PCEventQueue::schedule(PCEvent *event) bool PCEventQueue::doService(ThreadContext *tc) { - Addr pc = tc->instAddr() & ~0x3; + // This will fail to break on Alpha PALcode addresses, but that is + // a rare use case. + Addr pc = tc->instAddr(); int serviced = 0; range_t range = equal_range(pc); for (iterator i = range.first; i != range.second; ++i) { @@ -92,7 +94,7 @@ PCEventQueue::doService(ThreadContext *tc) // another event. This for example, prevents two invocations // of the SkipFuncEvent. Maybe we should have separate PC // event queues for each processor? - if (pc != (tc->instAddr() & ~0x3)) + if (pc != tc->instAddr()) continue; DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n", diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index dab1f766e..00e463de1 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -71,7 +71,7 @@ void PioDevice::init() { if (!pioPort) - panic("Pio port not connected to anything!"); + panic("Pio port of %s not connected to anything!", name()); pioPort->sendStatusChange(Port::RangeChange); } diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index dcc90e1bc..47ca32af2 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -905,7 +905,15 @@ class SimObject(object): for param in sorted(self._params.keys()): value = self._values.get(param) try: - d[param] = self._values[param].value + # Use native type for those supported by JSON and + # strings for everything else. skipkeys=True seems + # to not work as well as one would hope + if type(self._values[param].value) in \ + [str, unicode, int, long, float, bool, None]: + d[param] = self._values[param].value + else: + d[param] = str(self._values[param]) + except AttributeError: pass |