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-rw-r--r--src/arch/arm/isa/insts/misc.isa2
-rw-r--r--src/arch/arm/isa/templates/misc.isa2
-rw-r--r--src/arch/arm/tlb.cc3
-rw-r--r--src/arch/arm/tlb.hh3
-rw-r--r--src/mem/cache/cache_impl.hh28
-rw-r--r--src/mem/cache/tags/base.hh6
-rw-r--r--src/mem/cache/tags/fa_lru.cc8
-rw-r--r--src/mem/cache/tags/fa_lru.hh6
-rw-r--r--src/mem/cache/tags/iic.cc8
-rw-r--r--src/mem/cache/tags/iic.hh6
-rw-r--r--src/mem/cache/tags/lru.cc8
-rw-r--r--src/mem/cache/tags/lru.hh5
-rw-r--r--src/mem/request.hh3
13 files changed, 72 insertions, 16 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 2228a0f24..33197eaec 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -669,7 +669,7 @@ let {{
exec_output += PredOpExecute.subst(setendIop)
clrexCode = '''
- unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
+ unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
'''
clrexIop = InstObjParams("clrex", "Clrex","PredOp",
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index d2224dc6d..46af3f5b1 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -367,7 +367,7 @@ def template ClrexInitiateAcc {{
if (%(predicate_test)s)
{
if (fault == NoFault) {
- unsigned memAccessFlags = ArmISA::TLB::Clrex|3|Request::LLSC;
+ unsigned memAccessFlags = Request::CLREX|3|Request::LLSC;
fault = xc->read(0, (uint32_t&)Mem, memAccessFlags);
}
} else {
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a70a20518..a48805c81 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -358,9 +358,10 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
// If this is a clrex instruction, provide a PA of 0 with no fault
// This will force the monitor to set the tracked address to 0
// a bit of a hack but this effectively clrears this processors monitor
- if (flags & Clrex){
+ if (flags & Request::CLREX){
req->setPaddr(0);
req->setFlags(Request::UNCACHEABLE);
+ req->setFlags(Request::CLREX);
return NoFault;
}
if ((req->isInstFetch() && (!sctlr.i)) ||
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index d1ba42b39..1bddd8497 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -78,8 +78,7 @@ class TLB : public BaseTLB
// Because zero otherwise looks like a valid setting and may be used
// accidentally, this bit must be non-zero to show it was used on
// purpose.
- MustBeOne = 0x20,
- Clrex = 0x40
+ MustBeOne = 0x20
};
protected:
typedef std::multimap<Addr, int> PageTable;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index e472b2601..d471b293a 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -273,12 +273,14 @@ bool
Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
int &lat, PacketList &writebacks)
{
- int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
- blk = tags->accessBlock(pkt->getAddr(), lat, id);
-
- if (pkt->req->isUncacheable()) {
- if (blk != NULL) {
- tags->invalidateBlk(blk);
+ if (pkt->req->isUncacheable()) {
+ if (pkt->req->isClrex()) {
+ tags->clearLocks();
+ } else {
+ blk = tags->findBlock(pkt->getAddr());
+ if (blk != NULL) {
+ tags->invalidateBlk(blk);
+ }
}
blk = NULL;
@@ -286,6 +288,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
return false;
}
+ int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+ blk = tags->accessBlock(pkt->getAddr(), lat, id);
DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(),
pkt->req->isInstFetch() ? " (ifetch)" : "",
@@ -410,11 +414,13 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
}
if (pkt->req->isUncacheable()) {
- int lat = hitLatency;
- int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
- BlkType *blk = tags->accessBlock(pkt->getAddr(), lat, id);
- if (blk != NULL) {
- tags->invalidateBlk(blk);
+ if (pkt->req->isClrex()) {
+ tags->clearLocks();
+ } else {
+ BlkType *blk = tags->findBlock(pkt->getAddr());
+ if (blk != NULL) {
+ tags->invalidateBlk(blk);
+ }
}
// writes go in write buffer, reads use MSHR
diff --git a/src/mem/cache/tags/base.hh b/src/mem/cache/tags/base.hh
index fc8470290..62ae4a032 100644
--- a/src/mem/cache/tags/base.hh
+++ b/src/mem/cache/tags/base.hh
@@ -140,6 +140,12 @@ class BaseTags
* exits.
*/
virtual void cleanupRefs() {}
+
+ /**
+ *iterated through all blocks and clear all locks
+ *Needed to clear all lock tracking at once
+ */
+ virtual void clearLocks() {}
};
class BaseTagsCallback : public Callback
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index d13ba4973..4d1c2175f 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -286,3 +286,11 @@ FALRU::check()
}
return true;
}
+
+void
+FALRU::clearLocks()
+{
+ for (int i = 0; i < numBlocks; i++){
+ blks[i].clearLoadLocks();
+ }
+}
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 5047da12a..94ffeaa58 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -280,6 +280,12 @@ public:
{
return (tag);
}
+
+ /**
+ *iterated through all blocks and clear all locks
+ *Needed to clear all lock tracking at once
+ */
+ virtual void clearLocks();
};
#endif // __MEM_CACHE_TAGS_FA_LRU_HH__
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index f9afa5839..b5bd66366 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -632,6 +632,14 @@ IIC::invalidateBlk(IIC::BlkType *tag_ptr)
}
void
+IIC::clearLocks()
+{
+ for (int i = 0; i < numTags; i++){
+ tagStore[i].clearLoadLocks();
+ }
+}
+
+void
IIC::cleanupRefs()
{
for (unsigned i = 0; i < numTags; ++i) {
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh
index 5b12128c6..5553b8ca3 100644
--- a/src/mem/cache/tags/iic.hh
+++ b/src/mem/cache/tags/iic.hh
@@ -439,6 +439,11 @@ class IIC : public BaseTags
IICTag* findVictim(Addr addr, PacketList &writebacks);
void insertBlock(Addr addr, BlkType *blk, int context_src);
+ /**
+ *iterated through all blocks and clear all locks
+ *Needed to clear all lock tracking at once
+ */
+ virtual void clearLocks();
/**
* Called at end of simulation to complete average block reference stats.
@@ -497,6 +502,7 @@ private:
* @param data_ptr The data block to free.
*/
void freeDataBlock(unsigned long data_ptr);
+
};
#endif // __IIC_HH__
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index 0667c5428..a99936abf 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -217,6 +217,14 @@ LRU::invalidateBlk(BlkType *blk)
}
void
+LRU::clearLocks()
+{
+ for (int i = 0; i < numBlocks; i++){
+ blks[i].clearLoadLocks();
+ }
+}
+
+void
LRU::cleanupRefs()
{
for (unsigned i = 0; i < numSets*assoc; ++i) {
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index be8d75b5a..ff9811046 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -224,6 +224,11 @@ public:
{
return hitLatency;
}
+ /**
+ *iterated through all blocks and clear all locks
+ *Needed to clear all lock tracking at once
+ */
+ virtual void clearLocks();
/**
* Called at end of simulation to complete average block reference stats.
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 8d1697ad2..7149f3199 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -71,6 +71,8 @@ class Request : public FastAlloc
static const FlagsType UNCACHEABLE = 0x00001000;
/** This request is to a memory mapped register. */
static const FlagsType MMAPED_IPR = 0x00002000;
+ /** This request is a clear exclusive. */
+ static const FlagsType CLREX = 0x00004000;
/** The request should ignore unaligned access faults */
static const FlagsType NO_ALIGN_FAULT = 0x00020000;
@@ -456,6 +458,7 @@ class Request : public FastAlloc
bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); }
bool isMmapedIpr() const { return _flags.isSet(MMAPED_IPR); }
+ bool isClrex() const { return _flags.isSet(CLREX); }
bool
isMisaligned() const
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 16:58:06 +0000