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-rw-r--r--src/base/SConscript3
-rw-r--r--src/cpu/FuncUnit.py6
-rw-r--r--src/cpu/o3/fetch_impl.hh7
-rw-r--r--src/cpu/op_class.cc2
-rw-r--r--src/mem/bus.cc7
-rw-r--r--src/mem/bus.hh1
-rw-r--r--src/mem/cache/BaseCache.py3
-rw-r--r--src/python/m5/SimObject.py7
-rw-r--r--src/python/m5/__init__.py15
-rw-r--r--src/python/swig/sim_object.i1
10 files changed, 37 insertions, 15 deletions
diff --git a/src/base/SConscript b/src/base/SConscript
index cc9d06a0e..ca68bfb60 100644
--- a/src/base/SConscript
+++ b/src/base/SConscript
@@ -57,7 +57,8 @@ Source('circlebuf.cc')
Source('cprintf.cc')
Source('crc.cc')
Source('fast_alloc.cc')
-Source('fenv.c')
+if env['USE_FENV']:
+ Source('fenv.c')
Source('fifo_buffer.cc')
Source('hostinfo.cc')
Source('hybrid_pred.cc')
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index 541bdbd83..ad2d1b87b 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -29,15 +29,15 @@
from m5.SimObject import SimObject
from m5.params import *
-class OpType(Enum):
- vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
+class OpClass(Enum):
+ vals = ['No_OpClass', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
class OpDesc(SimObject):
type = 'OpDesc'
issueLat = Param.Int(1, "cycles until another can be issued")
- opClass = Param.OpType("type of operation")
+ opClass = Param.OpClass("type of operation")
opLat = Param.Int(1, "cycles until result is available")
class FUDesc(SimObject):
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 0d7403023..ff4617fcc 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -29,6 +29,9 @@
* Korey Sewell
*/
+#include <algorithm>
+#include <cstring>
+
#include "config/use_checker.hh"
#include "arch/isa_traits.hh"
@@ -48,8 +51,6 @@
#include "sim/system.hh"
#endif // FULL_SYSTEM
-#include <algorithm>
-
template<class Impl>
void
DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
@@ -374,7 +375,7 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
return;
}
- memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
+ memcpy(cacheData[tid], pkt->getPtr<uint8_t>(), cacheBlkSize);
cacheDataValid[tid] = true;
if (!drainPending) {
diff --git a/src/cpu/op_class.cc b/src/cpu/op_class.cc
index f7ef49c0f..02cb4a08a 100644
--- a/src/cpu/op_class.cc
+++ b/src/cpu/op_class.cc
@@ -34,7 +34,7 @@
const char *
opClassStrings[Num_OpClasses] =
{
- "(null)",
+ "No_OpClass",
"IntAlu",
"IntMult",
"IntDiv",
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 1f96115b8..13e545064 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -605,6 +605,13 @@ Bus::drain(Event * de)
}
}
+void
+Bus::startup()
+{
+ if (tickNextIdle < curTick)
+ tickNextIdle = (curTick / clock) * clock + clock;
+}
+
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
Param<int> bus_id;
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 5dd98c07e..ee647e20a 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -267,6 +267,7 @@ class Bus : public MemObject
virtual void deletePortRefs(Port *p);
virtual void init();
+ virtual void startup();
unsigned int drain(Event *de);
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 4b98f6b30..32f3f0174 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -27,6 +27,7 @@
# Authors: Nathan Binkert
from m5.params import *
+from m5.proxy import Self
from MemObject import MemObject
class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
@@ -77,7 +78,7 @@ class BaseCache(MemObject):
"Squash prefetches with a later time on a subsequent miss")
prefetch_degree = Param.Int(1,
"Degree of the prefetch depth")
- prefetch_latency = Param.Tick(10,
+ prefetch_latency = Param.Latency(10 * Self.latency,
"Latency of the prefetcher")
prefetch_policy = Param.Prefetch('none',
"Type of prefetcher to use")
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 42266a80e..f87e13732 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -722,6 +722,13 @@ class SimObject(object):
for child in self._children.itervalues():
child.resume()
+ def getMemoryMode(self):
+ if not isinstance(self, m5.objects.System):
+ return None
+
+ system_ptr = internal.sim_object.convertToSystemPtr(self._ccObject)
+ return system_ptr.getMemoryMode()
+
def changeTiming(self, mode):
if isinstance(self, m5.objects.System):
# i don't know if there's a better way to do this - calling
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index 06dc92bc6..a9206a474 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -190,17 +190,20 @@ def changeToAtomic(system):
if not isinstance(system, (objects.Root, objects.System)):
raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
(type(system), objects.Root, objects.System)
- doDrain(system)
- print "Changing memory mode to atomic"
- system.changeTiming(internal.sim_object.SimObject.Atomic)
+ if system.getMemoryMode() != internal.sim_object.SimObject.Atomic:
+ doDrain(system)
+ print "Changing memory mode to atomic"
+ system.changeTiming(internal.sim_object.SimObject.Atomic)
def changeToTiming(system):
if not isinstance(system, (objects.Root, objects.System)):
raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
(type(system), objects.Root, objects.System)
- doDrain(system)
- print "Changing memory mode to timing"
- system.changeTiming(internal.sim_object.SimObject.Timing)
+
+ if system.getMemoryMode() != internal.sim_object.SimObject.Timing:
+ doDrain(system)
+ print "Changing memory mode to timing"
+ system.changeTiming(internal.sim_object.SimObject.Timing)
def switchCpus(cpuList):
print "switching cpus"
diff --git a/src/python/swig/sim_object.i b/src/python/swig/sim_object.i
index b2af72c61..a1737c438 100644
--- a/src/python/swig/sim_object.i
+++ b/src/python/swig/sim_object.i
@@ -66,6 +66,7 @@ class System {
private:
System();
public:
+ SimObject::MemoryMode getMemoryMode();
void setMemoryMode(SimObject::MemoryMode mode);
};
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-15 03:12:19 +0000