4 files changed, 16 insertions, 16 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm
index 8032c0bec..f0301118c 100644
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm
@@ -32,8 +32,8 @@ machine(DMA, "DMA Controller")
   Cycles request_latency = 6
 {
 
-  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
-  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
+  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
+  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request";
 
   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -53,8 +53,8 @@ machine(DMA, "DMA Controller")
     void dataCallback(DataBlock);
   }
 
-  MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
-  State cur_state, no_vector="true";
+  MessageBuffer mandatoryQueue, ordered="false";
+  State cur_state;
 
   State getState(Address addr) {
     return cur_state;
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
index 5d67da465..7bc8a5f5d 100644
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -32,8 +32,8 @@ machine(DMA, "DMA Controller")
   Cycles request_latency = 6
 {
 
-  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
-  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
+  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
+  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request";
 
   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -48,8 +48,8 @@ machine(DMA, "DMA Controller")
     Ack,          desc="DMA write to memory completed";
   }
 
-  MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
-  State cur_state, no_vector="true";
+  MessageBuffer mandatoryQueue, ordered="false";
+  State cur_state;
 
   State getState(Address addr) {
     return cur_state;
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index 378344a09..d09a552db 100644
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -32,8 +32,8 @@ machine(DMA, "DMA Controller")
   Cycles request_latency = 6
 {
 
-  MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", vnet_type="response", no_vector="true";
-  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
+  MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", vnet_type="response";
+  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request";
 
   state_declaration(State, desc="DMA states", default="DMA_State_READY") {
     READY, AccessPermission:Invalid, desc="Ready to accept a new request";
@@ -53,8 +53,8 @@ machine(DMA, "DMA Controller")
     void dataCallback(DataBlock);
   }
 
-  MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
-  State cur_state, no_vector="true";
+  MessageBuffer mandatoryQueue, ordered="false";
+  State cur_state;
 
   State getState(Address addr) {
     return cur_state;
diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm
index fd7734677..fc4699fd3 100644
--- a/src/mem/protocol/MOESI_hammer-dma.sm
+++ b/src/mem/protocol/MOESI_hammer-dma.sm
@@ -32,8 +32,8 @@ machine(DMA, "DMA Controller")
   Cycles request_latency = 6
 {
 
-  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
-  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
+  MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
+  MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request";
 
   state_declaration(State, 
                     desc="DMA states", 
@@ -50,8 +50,8 @@ machine(DMA, "DMA Controller")
     Ack,          desc="DMA write to memory completed";
   }
 
-  MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
-  State cur_state, no_vector="true";
+  MessageBuffer mandatoryQueue, ordered="false";
+  State cur_state;
 
   State getState(Address addr) {
     return cur_state;