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-rw-r--r--src/arch/alpha/isa/decoder.isa2
-rw-r--r--src/arch/mips/isa/decoder.isa3
-rw-r--r--src/arch/sparc/isa/decoder.isa4
-rw-r--r--src/arch/x86/isa/decoder/two_byte_opcodes.isa2
-rw-r--r--src/cpu/base_dyn_inst.hh1
-rw-r--r--src/cpu/static_inst.hh4
6 files changed, 11 insertions, 5 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index af1a91a62..2177e8c4f 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -714,7 +714,7 @@ decode OPCODE default Unknown::unknown() {
}}, IsNonSpeculative);
0x83: callsys({{
xc->syscall(R0);
- }}, IsSerializeAfter, IsNonSpeculative);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
// Read uniq reg into ABI return value register (r0)
0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
// Write uniq reg with value from ABI arg register (r16)
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index e55d2e070..40ea223f6 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -134,7 +134,8 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
0x4: syscall({{ xc->syscall(R2); }},
- IsSerializeAfter, IsNonSpeculative);
+ IsSerializeAfter, IsNonSpeculative,
+ IsSyscall);
0x7: sync({{ ; }}, IsMemBarrier);
}
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 68b2183ad..14c652606 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1230,7 +1230,7 @@ decode OP default Unknown::unknown()
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
fault = new TrapInstruction(lTrapNum);
}
- }}, IsSerializeAfter, IsNonSpeculative);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
0x2: Trap::tccx({{
if(passesCondition(Ccr<7:4>, COND2))
{
@@ -1238,7 +1238,7 @@ decode OP default Unknown::unknown()
DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
fault = new TrapInstruction(lTrapNum);
}
- }}, IsSerializeAfter, IsNonSpeculative);
+ }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
}
0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
MemWriteOp);
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index a8c4e7062..e8307c6e6 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -70,7 +70,7 @@
#if FULL_SYSTEM
0x05: syscall();
#else
- 0x05: SyscallInst::syscall('xc->syscall(rax)');
+ 0x05: SyscallInst::syscall('xc->syscall(rax)', IsSyscall);
#endif
0x06: clts();
//sandpile.org says (AMD) after sysret, so I might want to check
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index a55c1e3c0..362babeff 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -498,6 +498,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
bool isQuiesce() const { return staticInst->isQuiesce(); }
bool isIprAccess() const { return staticInst->isIprAccess(); }
bool isUnverifiable() const { return staticInst->isUnverifiable(); }
+ bool isSyscall() const { return staticInst->isSyscall(); }
bool isMacroop() const { return staticInst->isMacroop(); }
bool isMicroop() const { return staticInst->isMicroop(); }
bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index b0a19c151..f32b61ee5 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -143,6 +143,9 @@ class StaticInstBase : public RefCounted
IsIprAccess, ///< Accesses IPRs
IsUnverifiable, ///< Can't be verified by a checker
+ IsSyscall, ///< Causes a system call to be emulated in syscall
+ /// emulation mode.
+
//Flags for microcode
IsMacroop, ///< Is a macroop containing microops
IsMicroop, ///< Is a microop
@@ -243,6 +246,7 @@ class StaticInstBase : public RefCounted
bool isQuiesce() const { return flags[IsQuiesce]; }
bool isIprAccess() const { return flags[IsIprAccess]; }
bool isUnverifiable() const { return flags[IsUnverifiable]; }
+ bool isSyscall() const { return flags[IsSyscall]; }
bool isMacroop() const { return flags[IsMacroop]; }
bool isMicroop() const { return flags[IsMicroop]; }
bool isDelayedCommit() const { return flags[IsDelayedCommit]; }