diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/sparc/tlb.cc | 2 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.cc | 6 |
2 files changed, 3 insertions, 5 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 41b0f2043..9d3b22657 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -1049,7 +1049,7 @@ doMmuReadError: Tick TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) { - uint64_t data = gtoh(pkt->get<uint64_t>()); + uint64_t data = pkt->get<uint64_t>(); Addr va = pkt->getAddr(); ASI asi = (ASI)pkt->req->getAsi(); diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index d96adffd5..f8819c734 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -450,6 +450,8 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) traceData->setData(data); } + data = htog(data); + //The block size of our peer. unsigned blockSize = dcachePort.peerBlockSize(); //The size of the data we're trying to read. @@ -496,10 +498,6 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) dcache_latency += TheISA::handleIprWrite(thread->getTC(), &pkt); } else { - //XXX This needs to be outside of the loop in order to - //work properly for cache line boundary crossing - //accesses in transendian simulations. - data = htog(data); if (hasPhysMemPort && pkt.getAddr() == physMemAddr) dcache_latency += physmemPort.sendAtomic(&pkt); else |