diff options
Diffstat (limited to 'src')
52 files changed, 683 insertions, 368 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 52e124ad5..fe70e4d16 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -338,6 +338,31 @@ decode OPCODE default Unknown::unknown() { 0x1c: decode INTFUNC { 0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); } 0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); } + + 0x30: ctpop({{ + uint64_t count = 0; + for (int i = 0; Rb<63:i>; ++i) { + if (Rb<i:i> == 0x1) + ++count; + } + Rc = count; + }}, IntAluOp); + + 0x31: perr({{ + uint64_t temp = 0; + int hi = 7; + int lo = 0; + for (int i = 0; i < 8; ++i) { + uint8_t ra_ub = Ra.uq<hi:lo>; + uint8_t rb_ub = Rb.uq<hi:lo>; + temp += (ra_ub >= rb_ub) ? + (ra_ub - rb_ub) : (rb_ub - ra_ub); + hi += 8; + lo += 8; + } + Rc = temp; + }}); + 0x32: ctlz({{ uint64_t count = 0; uint64_t temp = Rb; @@ -359,26 +384,163 @@ decode OPCODE default Unknown::unknown() { if (!(temp<7:0>)) { temp >>= 8; count += 8; } if (!(temp<3:0>)) { temp >>= 4; count += 4; } if (!(temp<1:0>)) { temp >>= 2; count += 2; } + if (!(temp<0:0> & ULL(0x1))) { + temp >>= 1; count += 1; + } if (!(temp<0:0> & ULL(0x1))) count += 1; Rc = count; }}, IntAluOp); - format FailUnimpl { - 0x30: ctpop(); - 0x31: perr(); - 0x34: unpkbw(); - 0x35: unpkbl(); - 0x36: pkwb(); - 0x37: pklb(); - 0x38: minsb8(); - 0x39: minsw4(); - 0x3a: minub8(); - 0x3b: minuw4(); - 0x3c: maxub8(); - 0x3d: maxuw4(); - 0x3e: maxsb8(); - 0x3f: maxsw4(); - } + + 0x34: unpkbw({{ + Rc = (Rb.uq<7:0> + | (Rb.uq<15:8> << 16) + | (Rb.uq<23:16> << 32) + | (Rb.uq<31:24> << 48)); + }}, IntAluOp); + + 0x35: unpkbl({{ + Rc = (Rb.uq<7:0> | (Rb.uq<15:8> << 32)); + }}, IntAluOp); + + 0x36: pkwb({{ + Rc = (Rb.uq<7:0> + | (Rb.uq<23:16> << 8) + | (Rb.uq<39:32> << 16) + | (Rb.uq<55:48> << 24)); + }}, IntAluOp); + + 0x37: pklb({{ + Rc = (Rb.uq<7:0> | (Rb.uq<39:32> << 8)); + }}, IntAluOp); + + 0x38: minsb8({{ + uint64_t temp = 0; + int hi = 63; + int lo = 56; + for (int i = 7; i >= 0; --i) { + int8_t ra_sb = Ra.uq<hi:lo>; + int8_t rb_sb = Rb.uq<hi:lo>; + temp = ((temp << 8) + | ((ra_sb < rb_sb) ? Ra.uq<hi:lo> + : Rb.uq<hi:lo>)); + hi -= 8; + lo -= 8; + } + Rc = temp; + }}); + + 0x39: minsw4({{ + uint64_t temp = 0; + int hi = 63; + int lo = 48; + for (int i = 3; i >= 0; --i) { + int16_t ra_sw = Ra.uq<hi:lo>; + int16_t rb_sw = Rb.uq<hi:lo>; + temp = ((temp << 16) + | ((ra_sw < rb_sw) ? Ra.uq<hi:lo> + : Rb.uq<hi:lo>)); + hi -= 16; + lo -= 16; + } + Rc = temp; + }}); + + 0x3a: minub8({{ + uint64_t temp = 0; + int hi = 63; + int lo = 56; + for (int i = 7; i >= 0; --i) { + uint8_t ra_ub = Ra.uq<hi:lo>; + uint8_t rb_ub = Rb.uq<hi:lo>; + temp = ((temp << 8) + | ((ra_ub < rb_ub) ? Ra.uq<hi:lo> + : Rb.uq<hi:lo>)); + hi -= 8; + lo -= 8; + } + Rc = temp; + }}); + + 0x3b: minuw4({{ + uint64_t temp = 0; + int hi = 63; + int lo = 48; + for (int i = 3; i >= 0; --i) { + uint16_t ra_sw = Ra.uq<hi:lo>; + uint16_t rb_sw = Rb.uq<hi:lo>; + temp = ((temp << 16) + | ((ra_sw < rb_sw) ? Ra.uq<hi:lo> + : Rb.uq<hi:lo>)); + hi -= 16; + lo -= 16; + } + Rc = temp; + }}); + + 0x3c: maxub8({{ + uint64_t temp = 0; + int hi = 63; + int lo = 56; + for (int i = 7; i >= 0; --i) { + uint8_t ra_ub = Ra.uq<hi:lo>; + uint8_t rb_ub = Rb.uq<hi:lo>; + temp = ((temp << 8) + | ((ra_ub > rb_ub) ? Ra.uq<hi:lo> + : Rb.uq<hi:lo>)); + hi -= 8; + lo -= 8; + } + Rc = temp; + }}); + + 0x3d: maxuw4({{ + uint64_t temp = 0; + int hi = 63; + int lo = 48; + for (int i = 3; i >= 0; --i) { + uint16_t ra_uw = Ra.uq<hi:lo>; + uint16_t rb_uw = Rb.uq<hi:lo>; + temp = ((temp << 16) + | ((ra_uw > rb_uw) ? Ra.uq<hi:lo> + : Rb.uq<hi:lo>)); + hi -= 16; + lo -= 16; + } + Rc = temp; + }}); + + 0x3e: maxsb8({{ + uint64_t temp = 0; + int hi = 63; + int lo = 56; + for (int i = 7; i >= 0; --i) { + int8_t ra_sb = Ra.uq<hi:lo>; + int8_t rb_sb = Rb.uq<hi:lo>; + temp = ((temp << 8) + | ((ra_sb > rb_sb) ? Ra.uq<hi:lo> + : Rb.uq<hi:lo>)); + hi -= 8; + lo -= 8; + } + Rc = temp; + }}); + + 0x3f: maxsw4({{ + uint64_t temp = 0; + int hi = 63; + int lo = 48; + for (int i = 3; i >= 0; --i) { + int16_t ra_sw = Ra.uq<hi:lo>; + int16_t rb_sw = Rb.uq<hi:lo>; + temp = ((temp << 16) + | ((ra_sw > rb_sw) ? Ra.uq<hi:lo> + : Rb.uq<hi:lo>)); + hi -= 16; + lo -= 16; + } + Rc = temp; + }}); format BasicOperateWithNopCheck { 0x70: decode RB { diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index 9d75d5fa1..1c83f64b2 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -175,21 +175,22 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize) void AlphaLiveProcess::startup() { - if (checkpointRestored) + ThreadContext *tc = system->getThreadContext(contextIds[0]); + tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); + + if (checkpointRestored) { return; + } Process::startup(); argsInit(MachineBytes, VMPageSize); - ThreadContext *tc = system->getThreadContext(contextIds[0]); tc->setIntReg(GlobalPointerReg, objFile->globalPointer()); //Operate in user mode tc->setMiscRegNoEffect(IPR_ICM, 0x18); //No super page mapping tc->setMiscRegNoEffect(IPR_MCSR, 0); - //Set this to 0 for now, but it should be unique for each process - tc->setMiscRegNoEffect(IPR_DTB_ASN, M5_pid << 57); } AlphaISA::IntReg diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 3c8c9a986..1cad7e4be 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -91,12 +91,6 @@ ISA::ISA() init(); } -ISA::ISA(BaseCPU *_cpu) -{ - cpu = _cpu; - init(); -} - void ISA::init() { @@ -173,11 +167,10 @@ ISA::expandForMultithreading(ThreadID num_threads, unsigned num_vpes) //@TODO: Use MIPS STYLE CONSTANTS (e.g. TCHALT_H instead of TCH_H) void ISA::reset(std::string core_name, ThreadID num_threads, - unsigned num_vpes, BaseCPU *_cpu) + unsigned num_vpes, BaseCPU *cpu) { DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n", num_threads, num_vpes); - cpu = _cpu; MipsISA::CoreSpecific &cp = cpu->coreParams; @@ -499,7 +492,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, miscRegFile[misc_reg][reg_sel] = cp0_val; - scheduleCP0Update(1); + scheduleCP0Update(tc->getCpuPtr(), 1); } /** @@ -528,7 +521,7 @@ ISA::filterCP0Write(int misc_reg, int reg_sel, const MiscReg &val) } void -ISA::scheduleCP0Update(int delay) +ISA::scheduleCP0Update(BaseCPU *cpu, int delay) { if (!cp0Updated) { cp0Updated = true; @@ -540,7 +533,7 @@ ISA::scheduleCP0Update(int delay) } void -ISA::updateCPU() +ISA::updateCPU(BaseCPU *cpu) { /////////////////////////////////////////////////////////////////// // @@ -578,7 +571,7 @@ ISA::CP0Event::process() switch (cp0EventType) { case UpdateCP0: - cp0->updateCPU(); + cp0->updateCPU(cpu); break; } } diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh index 165adff83..3f7afcdd0 100644 --- a/src/arch/mips/isa.hh +++ b/src/arch/mips/isa.hh @@ -64,18 +64,15 @@ namespace MipsISA std::vector<std::vector<MiscReg> > miscRegFile_WriteMask; std::vector<BankType> bankType; - BaseCPU *cpu; - public: ISA(); - ISA(BaseCPU *_cpu); void init(); void clear(unsigned tid_or_vpn = 0); void reset(std::string core_name, ThreadID num_threads, - unsigned num_vpes, BaseCPU *_cpu); + unsigned num_vpes, BaseCPU *cpu); void expandForMultithreading(ThreadID num_threads, unsigned num_vpes); @@ -147,11 +144,11 @@ namespace MipsISA }; // Schedule a CP0 Update Event - void scheduleCP0Update(int delay = 0); + void scheduleCP0Update(BaseCPU *cpu, int delay = 0); // If any changes have been made, then check the state for changes // and if necessary alert the CPU - void updateCPU(); + void updateCPU(BaseCPU *cpu); // Keep a List of CPU Events that need to be deallocated std::queue<CP0Event*> cp0EventRemoveList; diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index c531347d2..36533e076 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -2476,10 +2476,14 @@ decode OPCODE_HI default Unknown::unknown() { } } } - 0x3: decode OP_HI { - 0x2: decode OP_LO { - 0x3: FailUnimpl::rdhwr(); + 0x3: decode OP { +#if FULL_SYSTEM + 0x0: FailUnimpl::rdhwr(); +#else + 0x0: decode RD { + 29: BasicOp::rdhwr({{ Rt = TpValue; }}); } +#endif } } } diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index 50726cd30..27cb4357a 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -109,8 +109,11 @@ def operands {{ #LL Flag 'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1), + #Thread pointer value for SE mode + 'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1), + # Index Register - 'Index':('ControlReg','uw','MISCREG_INDEX',None,1), + 'Index': ('ControlReg','uw','MISCREG_INDEX',None,1), 'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1), diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc index c2a05b73b..4c3581ecb 100644 --- a/src/arch/mips/linux/process.cc +++ b/src/arch/mips/linux/process.cc @@ -126,6 +126,16 @@ sys_setsysinfoFunc(SyscallDesc *desc, int callnum, LiveProcess *process, return 1; } +static SyscallReturn +setThreadAreaFunc(SyscallDesc *desc, int callnum, LiveProcess *process, + ThreadContext *tc) +{ + int index = 0; + Addr addr = process->getSyscallArg(tc, index); + tc->setMiscRegNoEffect(MISCREG_TP_VALUE, addr); + return 0; +} + SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 0 */ SyscallDesc("syscall", unimplementedFunc), /* 1 */ SyscallDesc("exit", exitFunc), @@ -409,7 +419,44 @@ SyscallDesc MipsLinuxProcess::syscallDescs[] = { /* 279 */ SyscallDesc("unknown #279", unimplementedFunc), /* 280 */ SyscallDesc("add_key", unimplementedFunc), /* 281 */ SyscallDesc("request_key", unimplementedFunc), - /* 282 */ SyscallDesc("keyctl", unimplementedFunc) + /* 282 */ SyscallDesc("keyctl", unimplementedFunc), + /* 283 */ SyscallDesc("set_thread_area", setThreadAreaFunc), + /* 284 */ SyscallDesc("inotify_init", unimplementedFunc), + /* 285 */ SyscallDesc("inotify_add_watch", unimplementedFunc), + /* 286 */ SyscallDesc("inotify_rm_watch", unimplementedFunc), + /* 287 */ SyscallDesc("migrate_pages", unimplementedFunc), + /* 288 */ SyscallDesc("openat", unimplementedFunc), + /* 289 */ SyscallDesc("mkdirat", unimplementedFunc), + /* 290 */ SyscallDesc("mknodat", unimplementedFunc), + /* 291 */ SyscallDesc("fchownat", unimplementedFunc), + /* 292 */ SyscallDesc("futimesat", unimplementedFunc), + /* 293 */ SyscallDesc("fstatat64", unimplementedFunc), + /* 294 */ SyscallDesc("unlinkat", unimplementedFunc), + /* 295 */ SyscallDesc("renameat", unimplementedFunc), + /* 296 */ SyscallDesc("linkat", unimplementedFunc), + /* 297 */ SyscallDesc("symlinkat", unimplementedFunc), + /* 298 */ SyscallDesc("readlinkat", unimplementedFunc), + /* 299 */ SyscallDesc("fchmodat", unimplementedFunc), + /* 300 */ SyscallDesc("faccessat", unimplementedFunc), + /* 301 */ SyscallDesc("pselect6", unimplementedFunc), + /* 302 */ SyscallDesc("ppoll", unimplementedFunc), + /* 303 */ SyscallDesc("unshare", unimplementedFunc), + /* 304 */ SyscallDesc("splice", unimplementedFunc), + /* 305 */ SyscallDesc("sync_file_range", unimplementedFunc), + /* 306 */ SyscallDesc("tee", unimplementedFunc), + /* 307 */ SyscallDesc("vmsplice", unimplementedFunc), + /* 308 */ SyscallDesc("move_pages", unimplementedFunc), + /* 309 */ SyscallDesc("set_robust_list", unimplementedFunc), + /* 310 */ SyscallDesc("get_robust_list", unimplementedFunc), + /* 311 */ SyscallDesc("kexec_load", unimplementedFunc), + /* 312 */ SyscallDesc("getcpu", unimplementedFunc), + /* 313 */ SyscallDesc("epoll_pwait", unimplementedFunc), + /* 314 */ SyscallDesc("ioprio_set", unimplementedFunc), + /* 315 */ SyscallDesc("ioprio_get", unimplementedFunc), + /* 316 */ SyscallDesc("utimensat", unimplementedFunc), + /* 317 */ SyscallDesc("signalfd", unimplementedFunc), + /* 318 */ SyscallDesc("timerfd", unimplementedFunc), + /* 319 */ SyscallDesc("eventfd", unimplementedFunc) }; MipsLinuxProcess::MipsLinuxProcess(LiveProcessParams * params, diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index d96b0c81c..2fd9114e9 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -34,6 +34,7 @@ #include "arch/mips/process.hh" #include "base/loader/object_file.hh" +#include "base/loader/elf_object.hh" #include "base/misc.hh" #include "cpu/thread_context.hh" @@ -61,8 +62,8 @@ MipsLiveProcess::MipsLiveProcess(LiveProcessParams * params, brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); brk_point = roundUp(brk_point, VMPageSize); - // Set up region for mmaps. For now, start at bottom of kuseg space. - mmap_start = mmap_end = 0x10000; + // Set up region for mmaps. Start it 1GB above the top of the heap. + mmap_start = mmap_end = brk_point + 0x40000000L; } void @@ -70,18 +71,52 @@ MipsLiveProcess::startup() { Process::startup(); - argsInit(MachineBytes, VMPageSize); + argsInit<uint32_t>(VMPageSize); } +template<class IntType> void -MipsLiveProcess::argsInit(int intSize, int pageSize) +MipsLiveProcess::argsInit(int pageSize) { + int intSize = sizeof(IntType); + Process::startup(); + // load object file into target memory objFile->loadSections(initVirtMem); - // Calculate how much space we need for arg & env arrays. + typedef AuxVector<IntType> auxv_t; + std::vector<auxv_t> auxv; + + ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); + if (elfObject) + { + // Set the system page size + auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::VMPageSize)); + // Set the frequency at which time() increments + auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); + // For statically linked executables, this is the virtual + // address of the program header tables if they appear in the + // executable image. + auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); + DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable()); + // This is the size of a program header entry from the elf file. + auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); + // This is the number of program headers from the original elf file. + auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); + //The entry point to the program + auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); + //Different user and group IDs + auxv.push_back(auxv_t(M5_AT_UID, uid())); + auxv.push_back(auxv_t(M5_AT_EUID, euid())); + auxv.push_back(auxv_t(M5_AT_GID, gid())); + auxv.push_back(auxv_t(M5_AT_EGID, egid())); + } + + // Calculate how much space we need for arg & env & auxv arrays. int argv_array_size = intSize * (argv.size() + 1); int envp_array_size = intSize * (envp.size() + 1); + int auxv_array_size = intSize * 2 * (auxv.size() + 1); + int arg_data_size = 0; for (vector<string>::size_type i = 0; i < argv.size(); ++i) { arg_data_size += argv[i].size() + 1; @@ -92,9 +127,11 @@ MipsLiveProcess::argsInit(int intSize, int pageSize) } int space_needed = - argv_array_size + envp_array_size + arg_data_size + env_data_size; - if (space_needed < 32*1024) - space_needed = 32*1024; + argv_array_size + + envp_array_size + + auxv_array_size + + arg_data_size + + env_data_size; // set bottom of stack stack_min = stack_base - space_needed; @@ -105,27 +142,16 @@ MipsLiveProcess::argsInit(int intSize, int pageSize) pTable->allocate(stack_min, roundUp(stack_size, pageSize)); // map out initial stack contents - // ======== - // NOTE: Using uint32_t hardcodes MIPS32 and not MIPS64 - // even if MIPS64 was intended. This is because the - // copyStringArray function templates on the parameters. - // Elegant way to check intSize and vary between 32/64? - // ======== - uint32_t argv_array_base = stack_min + intSize; // room for argc - uint32_t envp_array_base = argv_array_base + argv_array_size; - uint32_t arg_data_base = envp_array_base + envp_array_size; - uint32_t env_data_base = arg_data_base + arg_data_size; + IntType argv_array_base = stack_min + intSize; // room for argc + IntType envp_array_base = argv_array_base + argv_array_size; + IntType auxv_array_base = envp_array_base + envp_array_size; + IntType arg_data_base = auxv_array_base + auxv_array_size; + IntType env_data_base = arg_data_base + arg_data_size; // write contents to stack - uint32_t argc = argv.size(); - - if (intSize == 8) - argc = htog((uint64_t)argc); - else if (intSize == 4) - argc = htog((uint32_t)argc); - else - panic("Unknown int size"); + IntType argc = argv.size(); + argc = htog((IntType)argc); initVirtMem->writeBlob(stack_min, (uint8_t*)&argc, intSize); @@ -133,6 +159,21 @@ MipsLiveProcess::argsInit(int intSize, int pageSize) copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); + // Copy the aux vector + for (typename vector<auxv_t>::size_type x = 0; x < auxv.size(); x++) { + initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize, + (uint8_t*)&(auxv[x].a_type), intSize); + initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize, + (uint8_t*)&(auxv[x].a_val), intSize); + } + + // Write out the terminating zeroed auxilliary vector + for (unsigned i = 0; i < 2; i++) { + const IntType zero = 0; + const Addr addr = auxv_array_base + 2 * intSize * (auxv.size() + i); + initVirtMem->writeBlob(addr, (uint8_t*)&zero, intSize); + } + ThreadContext *tc = system->getThreadContext(contextIds[0]); setSyscallArg(tc, 0, argc); diff --git a/src/arch/mips/process.hh b/src/arch/mips/process.hh index f35ec8554..f1238b41f 100644 --- a/src/arch/mips/process.hh +++ b/src/arch/mips/process.hh @@ -47,7 +47,8 @@ class MipsLiveProcess : public LiveProcess void startup(); - void argsInit(int intSize, int pageSize); + template<class IntType> + void argsInit(int pageSize); public: MipsISA::IntReg getSyscallArg(ThreadContext *tc, int &i); diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh index fdb04b131..5cf76634d 100644 --- a/src/arch/mips/registers.hh +++ b/src/arch/mips/registers.hh @@ -275,6 +275,7 @@ enum MiscRegIndex{ MISCREG_DESAVE = 248, //Bank 31: 248-256 MISCREG_LLFLAG = 257, + MISCREG_TP_VALUE, MISCREG_NUMREGS }; diff --git a/src/arch/x86/insts/micromediaop.hh b/src/arch/x86/insts/micromediaop.hh index 508ef4e26..854d4de09 100644 --- a/src/arch/x86/insts/micromediaop.hh +++ b/src/arch/x86/insts/micromediaop.hh @@ -35,6 +35,12 @@ namespace X86ISA { + enum MediaFlag { + MediaMultHiOp = 1, + MediaSignedOp = 64, + MediaScalarOp = 128 + }; + class MediaOpBase : public X86MicroopBase { protected: @@ -59,6 +65,30 @@ namespace X86ISA src1(_src1.idx), dest(_dest.idx), srcSize(_srcSize), destSize(_destSize), ext(_ext) {} + + bool + scalarOp() const + { + return ext & MediaScalarOp; + } + + int + numItems(int size) const + { + return scalarOp() ? 1 : (sizeof(FloatRegBits) / size); + } + + bool + multHi() const + { + return ext & MediaMultHiOp; + } + + bool + signedOp() const + { + return ext & MediaSignedOp; + } }; class MediaOpReg : public MediaOpBase diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py index 083d8775d..e4c90b8d9 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/addition.py @@ -55,33 +55,33 @@ microcode = ''' def macroop ADDSS_XMM_XMM { - maddf xmml, xmml, xmmlm, size=4, ext=1 + maddf xmml, xmml, xmmlm, size=4, ext=Scalar }; def macroop ADDSS_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - maddf xmml, xmml, ufp1, size=4, ext=1 + maddf xmml, xmml, ufp1, size=4, ext=Scalar }; def macroop ADDSS_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - maddf xmml, xmml, ufp1, size=4, ext=1 + maddf xmml, xmml, ufp1, size=4, ext=Scalar }; def macroop ADDSD_XMM_XMM { - maddf xmml, xmml, xmmlm, size=8, ext=1 + maddf xmml, xmml, xmmlm, size=8, ext=Scalar }; def macroop ADDSD_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - maddf xmml, xmml, ufp1, size=8, ext=1 + maddf xmml, xmml, ufp1, size=8, ext=Scalar }; def macroop ADDSD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - maddf xmml, xmml, ufp1, size=8, ext=1 + maddf xmml, xmml, ufp1, size=8, ext=Scalar }; def macroop ADDPS_XMM_XMM { diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py index 3e565278c..e8f596463 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/division.py @@ -55,33 +55,33 @@ microcode = ''' def macroop DIVSS_XMM_XMM { - mdivf xmml, xmml, xmmlm, size=4, ext=1 + mdivf xmml, xmml, xmmlm, size=4, ext=Scalar }; def macroop DIVSS_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mdivf xmml, xmml, ufp1, size=4, ext=1 + mdivf xmml, xmml, ufp1, size=4, ext=Scalar }; def macroop DIVSS_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mdivf xmml, xmml, ufp1, size=4, ext=1 + mdivf xmml, xmml, ufp1, size=4, ext=Scalar }; def macroop DIVSD_XMM_XMM { - mdivf xmml, xmml, xmmlm, size=8, ext=1 + mdivf xmml, xmml, xmmlm, size=8, ext=Scalar }; def macroop DIVSD_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mdivf xmml, xmml, ufp1, size=8, ext=1 + mdivf xmml, xmml, ufp1, size=8, ext=Scalar }; def macroop DIVSD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mdivf xmml, xmml, ufp1, size=8, ext=1 + mdivf xmml, xmml, ufp1, size=8, ext=Scalar }; def macroop DIVPS_XMM_XMM { diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py index adf7650b9..41c5f719c 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/horizontal_addition.py @@ -57,23 +57,23 @@ microcode = ''' # HADDPS def macroop HADDPD_XMM_XMM { - maddf ufp1, xmmh , xmml, size=8, ext=1 - maddf xmmh, xmmlm, xmmhm, size=8, ext=1 + maddf ufp1, xmmh , xmml, size=8, ext=Scalar + maddf xmmh, xmmlm, xmmhm, size=8, ext=Scalar movfp xmml, ufp1 }; def macroop HADDPD_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT+8", dataSize=8 - maddf xmml, xmmh, xmml, size=8, ext=1 - maddf xmmh, ufp1, ufp2, size=8, ext=1 + maddf xmml, xmmh, xmml, size=8, ext=Scalar + maddf xmmh, ufp1, ufp2, size=8, ext=Scalar }; def macroop HADDPD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT+8", dataSize=8 - maddf xmml, xmmh, xmml, size=8, ext=1 - maddf xmmh, ufp1, ufp2, size=8, ext=1 + maddf xmml, xmmh, xmml, size=8, ext=Scalar + maddf xmmh, ufp1, ufp2, size=8, ext=Scalar }; ''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py index fc28fbda4..c00aa6048 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/multiplication.py @@ -55,33 +55,33 @@ microcode = ''' def macroop MULSS_XMM_XMM { - mmulf xmml, xmml, xmmlm, size=4, ext=1 + mmulf xmml, xmml, xmmlm, size=4, ext=Scalar }; def macroop MULSS_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mmulf xmml, xmml, ufp1, size=4, ext=1 + mmulf xmml, xmml, ufp1, size=4, ext=Scalar }; def macroop MULSS_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mmulf xmml, xmml, ufp1, size=4, ext=1 + mmulf xmml, xmml, ufp1, size=4, ext=Scalar }; def macroop MULSD_XMM_XMM { - mmulf xmml, xmml, xmmlm, size=8, ext=1 + mmulf xmml, xmml, xmmlm, size=8, ext=Scalar }; def macroop MULSD_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mmulf xmml, xmml, ufp1, size=8, ext=1 + mmulf xmml, xmml, ufp1, size=8, ext=Scalar }; def macroop MULSD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mmulf xmml, xmml, ufp1, size=8, ext=1 + mmulf xmml, xmml, ufp1, size=8, ext=Scalar }; def macroop MULPS_XMM_XMM { diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py index fdeb30ddc..dc52a63c3 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/square_root.py @@ -55,18 +55,18 @@ microcode = ''' def macroop SQRTSS_XMM_XMM { - msqrt xmml, xmmlm, size=4, ext=1 + msqrt xmml, xmmlm, size=4, ext=Scalar }; def macroop SQRTSS_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - msqrt xmml, ufp1, size=4, ext=1 + msqrt xmml, ufp1, size=4, ext=Scalar }; def macroop SQRTSS_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - msqrt xmml, ufp1, size=4, ext=1 + msqrt xmml, ufp1, size=4, ext=Scalar }; def macroop SQRTPS_XMM_XMM { @@ -90,18 +90,18 @@ def macroop SQRTPS_XMM_P { }; def macroop SQRTSD_XMM_XMM { - msqrt xmml, xmmlm, size=8, ext=1 + msqrt xmml, xmmlm, size=8, ext=Scalar }; def macroop SQRTSD_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - msqrt xmml, ufp1, size=8, ext=1 + msqrt xmml, ufp1, size=8, ext=Scalar }; def macroop SQRTSD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - msqrt xmml, ufp1, size=8, ext=1 + msqrt xmml, ufp1, size=8, ext=Scalar }; def macroop SQRTPD_XMM_XMM { diff --git a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py index 378abc070..d69ce3831 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/subtraction.py @@ -55,33 +55,33 @@ microcode = ''' def macroop SUBSS_XMM_XMM { - msubf xmml, xmml, xmmlm, size=4, ext=1 + msubf xmml, xmml, xmmlm, size=4, ext=Scalar }; def macroop SUBSS_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - msubf xmml, xmml, ufp1, size=4, ext=1 + msubf xmml, xmml, ufp1, size=4, ext=Scalar }; def macroop SUBSS_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - msubf xmml, xmml, ufp1, size=4, ext=1 + msubf xmml, xmml, ufp1, size=4, ext=Scalar }; def macroop SUBSD_XMM_XMM { - msubf xmml, xmml, xmmlm, size=8, ext=1 + msubf xmml, xmml, xmmlm, size=8, ext=Scalar }; def macroop SUBSD_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - msubf xmml, xmml, ufp1, size=8, ext=1 + msubf xmml, xmml, ufp1, size=8, ext=Scalar }; def macroop SUBSD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - msubf xmml, xmml, ufp1, size=8, ext=1 + msubf xmml, xmml, ufp1, size=8, ext=Scalar }; def macroop SUBPS_XMM_XMM { diff --git a/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_mask.py b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_mask.py index 09c34600b..e4449be10 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_mask.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_mask.py @@ -95,32 +95,32 @@ def macroop CMPPD_XMM_P_I { }; def macroop CMPSS_XMM_XMM_I { - mcmpf2r xmml, xmml, xmmlm, size=4, ext="IMMEDIATE | 0x8" + mcmpf2r xmml, xmml, xmmlm, size=4, ext="IMMEDIATE |" + Scalar }; def macroop CMPSS_XMM_M_I { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 - mcmpf2r xmml, xmml, ufp1, size=4, ext="IMMEDIATE | 0x8" + mcmpf2r xmml, xmml, ufp1, size=4, ext="IMMEDIATE |" + Scalar }; def macroop CMPSS_XMM_P_I { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 - mcmpf2r xmml, xmml, ufp1, size=4, ext="IMMEDIATE | 0x8" + mcmpf2r xmml, xmml, ufp1, size=4, ext="IMMEDIATE |" + Scalar }; def macroop CMPSD_XMM_XMM_I { - mcmpf2r xmml, xmml, xmmlm, size=8, ext="IMMEDIATE | 0x8" + mcmpf2r xmml, xmml, xmmlm, size=8, ext="IMMEDIATE |" + Scalar }; def macroop CMPSD_XMM_M_I { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 - mcmpf2r xmml, xmml, ufp1, size=8, ext="IMMEDIATE | 0x8" + mcmpf2r xmml, xmml, ufp1, size=8, ext="IMMEDIATE |" + Scalar }; def macroop CMPSD_XMM_P_I { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 - mcmpf2r xmml, xmml, ufp1, size=8, ext="IMMEDIATE | 0x8" + mcmpf2r xmml, xmml, ufp1, size=8, ext="IMMEDIATE |" + Scalar }; ''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py index 17c97662c..0a62ce343 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/compare/compare_and_write_minimum_or_maximum.py @@ -95,33 +95,33 @@ def macroop MINPD_XMM_P { }; def macroop MINSS_XMM_XMM { - mminf xmml, xmml, xmmlm, ext=1, size=4 + mminf xmml, xmml, xmmlm, ext=Scalar, size=4 }; def macroop MINSS_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 - mminf xmml, xmml, ufp1, ext=1, size=4 + mminf xmml, xmml, ufp1, ext=Scalar, size=4 }; def macroop MINSS_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 - mminf xmml, xmml, ufp1, ext=1, size=4 + mminf xmml, xmml, ufp1, ext=Scalar, size=4 }; def macroop MINSD_XMM_XMM { - mminf xmml, xmml, xmmlm, ext=1, size=8 + mminf xmml, xmml, xmmlm, ext=Scalar, size=8 }; def macroop MINSD_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 - mminf xmml, xmml, ufp1, ext=1, size=8 + mminf xmml, xmml, ufp1, ext=Scalar, size=8 }; def macroop MINSD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 - mminf xmml, xmml, ufp1, ext=1, size=8 + mminf xmml, xmml, ufp1, ext=Scalar, size=8 }; def macroop MAXPS_XMM_XMM { @@ -165,32 +165,32 @@ def macroop MAXPD_XMM_P { }; def macroop MAXSS_XMM_XMM { - mmaxf xmml, xmml, xmmlm, ext=1, size=4 + mmaxf xmml, xmml, xmmlm, ext=Scalar, size=4 }; def macroop MAXSS_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 - mmaxf xmml, xmml, ufp1, ext=1, size=4 + mmaxf xmml, xmml, ufp1, ext=Scalar, size=4 }; def macroop MAXSS_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 - mmaxf xmml, xmml, ufp1, ext=1, size=4 + mmaxf xmml, xmml, ufp1, ext=Scalar, size=4 }; def macroop MAXSD_XMM_XMM { - mmaxf xmml, xmml, xmmlm, ext=1, size=8 + mmaxf xmml, xmml, xmmlm, ext=Scalar, size=8 }; def macroop MAXSD_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 - mmaxf xmml, xmml, ufp1, ext=1, size=8 + mmaxf xmml, xmml, ufp1, ext=Scalar, size=8 }; def macroop MAXSD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 - mmaxf xmml, xmml, ufp1, ext=1, size=8 + mmaxf xmml, xmml, ufp1, ext=Scalar, size=8 }; ''' diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py index 1c36f7e45..5988c77ba 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_floating_point.py @@ -55,33 +55,33 @@ microcode = ''' def macroop CVTSS2SD_XMM_XMM { - cvtf2f xmml, xmmlm, destSize=8, srcSize=4, ext=1 + cvtf2f xmml, xmmlm, destSize=8, srcSize=4, ext=Scalar }; def macroop CVTSS2SD_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - cvtf2f xmml, ufp1, destSize=8, srcSize=4, ext=1 + cvtf2f xmml, ufp1, destSize=8, srcSize=4, ext=Scalar }; def macroop CVTSS2SD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - cvtf2f xmml, ufp1, destSize=8, srcSize=4, ext=1 + cvtf2f xmml, ufp1, destSize=8, srcSize=4, ext=Scalar }; def macroop CVTSD2SS_XMM_XMM { - cvtf2f xmml, xmmlm, destSize=4, srcSize=8, ext=1 + cvtf2f xmml, xmmlm, destSize=4, srcSize=8, ext=Scalar }; def macroop CVTSD2SS_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - cvtf2f xmml, ufp1, destSize=4, srcSize=8, ext=1 + cvtf2f xmml, ufp1, destSize=4, srcSize=8, ext=Scalar }; def macroop CVTSD2SS_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - cvtf2f xmml, ufp1, destSize=4, srcSize=8, ext=1 + cvtf2f xmml, ufp1, destSize=4, srcSize=8, ext=Scalar }; def macroop CVTPS2PD_XMM_XMM { diff --git a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py index 16abd96f4..0b7ca5c5b 100644 --- a/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py +++ b/src/arch/x86/isa/insts/simd128/floating_point/data_conversion/convert_floating_point_to_gpr_integer.py @@ -55,74 +55,74 @@ microcode = ''' def macroop CVTSS2SI_R_XMM { - cvtf2i ufp1, xmmlm, srcSize=4, destSize=dsz, ext=(1 | 4) + cvtf2i ufp1, xmmlm, srcSize=4, destSize=dsz, ext = Scalar + "| 4" mov2int reg, ufp1, size=dsz }; def macroop CVTSS2SI_R_M { ldfp ufp1, seg, sib, disp, dataSize=8 - cvtf2i ufp1, ufp1, srcSize=4, destSize=dsz, ext=(1 | 4) + cvtf2i ufp1, ufp1, srcSize=4, destSize=dsz, ext = Scalar + "| 4" mov2int reg, ufp1, size=dsz }; def macroop CVTSS2SI_R_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - cvtf2i ufp1, ufp1, srcSize=4, destSize=dsz, ext=(1 | 4) + cvtf2i ufp1, ufp1, srcSize=4, destSize=dsz, ext = Scalar + "| 4" mov2int reg, ufp1, size=dsz }; def macroop CVTSD2SI_R_XMM { - cvtf2i ufp1, xmmlm, srcSize=8, destSize=dsz, ext=(1 | 4) + cvtf2i ufp1, xmmlm, srcSize=8, destSize=dsz, ext = Scalar + "| 4" mov2int reg, ufp1, size=dsz }; def macroop CVTSD2SI_R_M { ldfp ufp1, seg, sib, disp, dataSize=8 - cvtf2i ufp1, ufp1, srcSize=8, destSize=dsz, ext=(1 | 4) + cvtf2i ufp1, ufp1, srcSize=8, destSize=dsz, ext = Scalar + "| 4" mov2int reg, ufp1, size=dsz }; def macroop CVTSD2SI_R_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - cvtf2i ufp1, ufp1, srcSize=8, destSize=dsz, ext=(1 | 4) + cvtf2i ufp1, ufp1, srcSize=8, destSize=dsz, ext = Scalar + "| 4" mov2int reg, ufp1, size=dsz }; def macroop CVTTSS2SI_R_XMM { - cvtf2i ufp1, xmmlm, srcSize=4, destSize=dsz, ext=1 + cvtf2i ufp1, xmmlm, srcSize=4, destSize=dsz, ext=Scalar mov2int reg, ufp1, size=dsz }; def macroop CVTTSS2SI_R_M { ldfp ufp1, seg, sib, disp, dataSize=8 - cvtf2i ufp1, ufp1, srcSize=4, destSize=dsz, ext=1 + cvtf2i ufp1, ufp1, srcSize=4, destSize=dsz, ext=Scalar mov2int reg, ufp1, size=dsz }; def macroop CVTTSS2SI_R_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - cvtf2i ufp1, ufp1, srcSize=4, destSize=dsz, ext=1 + cvtf2i ufp1, ufp1, srcSize=4, destSize=dsz, ext=Scalar mov2int reg, ufp1, size=dsz }; def macroop CVTTSD2SI_R_XMM { - cvtf2i ufp1, xmmlm, srcSize=8, destSize=dsz, ext=1 + cvtf2i ufp1, xmmlm, srcSize=8, destSize=dsz, ext=Scalar mov2int reg, ufp1, size=dsz }; def macroop CVTTSD2SI_R_M { ldfp ufp1, seg, sib, disp, dataSize=8 - cvtf2i ufp1, ufp1, srcSize=8, destSize=dsz, ext=1 + cvtf2i ufp1, ufp1, srcSize=8, destSize=dsz, ext=Scalar mov2int reg, ufp1, size=dsz }; def macroop CVTTSD2SI_R_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - cvtf2i ufp1, ufp1, srcSize=8, destSize=dsz, ext=1 + cvtf2i ufp1, ufp1, srcSize=8, destSize=dsz, ext=Scalar mov2int reg, ufp1, size=dsz }; ''' diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py index 05e2b80d5..1e9856562 100644 --- a/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/addition.py @@ -135,43 +135,43 @@ def macroop PADDQ_XMM_P { }; def macroop PADDSB_XMM_XMM { - maddi xmml, xmml, xmmlm, size=1, ext=4 - maddi xmmh, xmmh, xmmhm, size=1, ext=4 + maddi xmml, xmml, xmmlm, size=1, ext = "2 |" + Signed + maddi xmmh, xmmh, xmmhm, size=1, ext = "2 |" + Signed }; def macroop PADDSB_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - maddi xmml, xmml, ufp1, size=1, ext=4 - maddi xmmh, xmmh, ufp2, size=1, ext=4 + maddi xmml, xmml, ufp1, size=1, ext = "2 |" + Signed + maddi xmmh, xmmh, ufp2, size=1, ext = "2 |" + Signed }; def macroop PADDSB_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - maddi xmml, xmml, ufp1, size=1, ext=4 - maddi xmmh, xmmh, ufp2, size=1, ext=4 + maddi xmml, xmml, ufp1, size=1, ext = "2 |" + Signed + maddi xmmh, xmmh, ufp2, size=1, ext = "2 |" + Signed }; def macroop PADDSW_XMM_XMM { - maddi xmml, xmml, xmmlm, size=2, ext=4 - maddi xmmh, xmmh, xmmhm, size=2, ext=4 + maddi xmml, xmml, xmmlm, size=2, ext = "2 |" + Signed + maddi xmmh, xmmh, xmmhm, size=2, ext = "2 |" + Signed }; def macroop PADDSW_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - maddi xmml, xmml, ufp1, size=2, ext=4 - maddi xmmh, xmmh, ufp2, size=2, ext=4 + maddi xmml, xmml, ufp1, size=2, ext = "2 |" + Signed + maddi xmmh, xmmh, ufp2, size=2, ext = "2 |" + Signed }; def macroop PADDSW_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - maddi xmml, xmml, ufp1, size=2, ext=4 - maddi xmmh, xmmh, ufp2, size=2, ext=4 + maddi xmml, xmml, ufp1, size=2, ext = "2 |" + Signed + maddi xmmh, xmmh, ufp2, size=2, ext = "2 |" + Signed }; def macroop PADDUSB_XMM_XMM { diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py index a5d90c6b2..904bf69f8 100644 --- a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiplication.py @@ -55,82 +55,82 @@ microcode = ''' def macroop PMULHW_XMM_XMM { - mmuli xmml, xmml, xmmlm, size=2, ext=(0x2 | 0x8) - mmuli xmmh, xmmh, xmmhm, size=2, ext=(0x2 | 0x8) + mmuli xmml, xmml, xmmlm, size=2, ext = Signed + "|" + MultHi + mmuli xmmh, xmmh, xmmhm, size=2, ext = Signed + "|" + MultHi }; def macroop PMULHW_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - mmuli xmml, xmml, ufp1, size=2, ext=(0x2 | 0x8) - mmuli xmmh, xmmh, ufp2, size=2, ext=(0x2 | 0x8) + mmuli xmml, xmml, ufp1, size=2, ext = Signed + "|" + MultHi + mmuli xmmh, xmmh, ufp2, size=2, ext = Signed + "|" + MultHi }; def macroop PMULHW_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - mmuli xmml, xmml, ufp1, size=2, ext=(0x2 | 0x8) - mmuli xmmh, xmmh, ufp2, size=2, ext=(0x2 | 0x8) + mmuli xmml, xmml, ufp1, size=2, ext = Signed + "|" + MultHi + mmuli xmmh, xmmh, ufp2, size=2, ext = Signed + "|" + MultHi }; def macroop PMULLW_XMM_XMM { - mmuli xmml, xmml, xmmlm, size=2, ext=2 - mmuli xmmh, xmmh, xmmhm, size=2, ext=2 + mmuli xmml, xmml, xmmlm, size=2, ext=Signed + mmuli xmmh, xmmh, xmmhm, size=2, ext=Signed }; def macroop PMULLW_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - mmuli xmml, xmml, ufp1, size=2, ext=2 - mmuli xmmh, xmmh, ufp2, size=2, ext=2 + mmuli xmml, xmml, ufp1, size=2, ext=Signed + mmuli xmmh, xmmh, ufp2, size=2, ext=Signed }; def macroop PMULLW_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - mmuli xmml, xmml, ufp1, size=2, ext=2 - mmuli xmmh, xmmh, ufp2, size=2, ext=2 + mmuli xmml, xmml, ufp1, size=2, ext=Signed + mmuli xmmh, xmmh, ufp2, size=2, ext=Signed }; def macroop PMULHUW_XMM_XMM { - mmuli xmml, xmml, xmmlm, size=2, ext=8 - mmuli xmmh, xmmh, xmmhm, size=2, ext=8 + mmuli xmml, xmml, xmmlm, size=2, ext = MultHi + mmuli xmmh, xmmh, xmmhm, size=2, ext = MultHi }; def macroop PMULHUW_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - mmuli xmml, xmml, ufp1, size=2, ext=8 - mmuli xmmh, xmmh, ufp2, size=2, ext=8 + mmuli xmml, xmml, ufp1, size=2, ext = MultHi + mmuli xmmh, xmmh, ufp2, size=2, ext = MultHi }; def macroop PMULHUW_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - mmuli xmml, xmml, ufp1, size=2, ext=8 - mmuli xmmh, xmmh, ufp2, size=2, ext=8 + mmuli xmml, xmml, ufp1, size=2, ext = MultHi + mmuli xmmh, xmmh, ufp2, size=2, ext = MultHi }; def macroop PMULUDQ_XMM_XMM { - mmuli xmml, xmml, xmmlm, srcSize=4, destSize=8, ext=1 - mmuli xmmh, xmmh, xmmhm, srcSize=4, destSize=8, ext=1 + mmuli xmml, xmml, xmmlm, srcSize=4, destSize=8, ext=Scalar + mmuli xmmh, xmmh, xmmhm, srcSize=4, destSize=8, ext=Scalar }; def macroop PMULUDQ_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - mmuli xmml, xmml, ufp1, srcSize=4, destSize=8, ext=1 - mmuli xmmh, xmmh, ufp2, srcSize=4, destSize=8, ext=1 + mmuli xmml, xmml, ufp1, srcSize=4, destSize=8, ext=Scalar + mmuli xmmh, xmmh, ufp2, srcSize=4, destSize=8, ext=Scalar }; def macroop PMULUDQ_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - mmuli xmml, xmml, ufp1, srcSize=4, destSize=8, ext=1 - mmuli xmmh, xmmh, ufp2, srcSize=4, destSize=8, ext=1 + mmuli xmml, xmml, ufp1, srcSize=4, destSize=8, ext=Scalar + mmuli xmmh, xmmh, ufp2, srcSize=4, destSize=8, ext=Scalar }; ''' diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py index f157d165f..64ae05190 100644 --- a/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/multiply_add.py @@ -55,22 +55,22 @@ microcode = ''' def macroop PMADDWD_XMM_XMM { - mmuli ufp3, xmml, xmmlm, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20) - mmuli ufp4, xmml, xmmlm, srcSize=2, destSize=4, ext=(0x2 | 0x10) + mmuli ufp3, xmml, xmmlm, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 0x20" + mmuli ufp4, xmml, xmmlm, srcSize=2, destSize=4, ext = Signed + "| 0x10" maddi xmml, ufp3, ufp4, size=4, ext=0 - mmuli ufp3, xmmh, xmmhm, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20) - mmuli ufp4, xmmh, xmmhm, srcSize=2, destSize=4, ext=(0x2 | 0x10) + mmuli ufp3, xmmh, xmmhm, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 0x20" + mmuli ufp4, xmmh, xmmhm, srcSize=2, destSize=4, ext = Signed + "| 0x10" maddi xmmh, ufp3, ufp4, size=4, ext=0 }; def macroop PMADDWD_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - mmuli ufp3, xmml, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20) - mmuli ufp4, xmml, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10) + mmuli ufp3, xmml, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 0x20" + mmuli ufp4, xmml, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10" maddi xmml, ufp3, ufp4, size=4, ext=0 - mmuli ufp3, xmmh, ufp2, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20) - mmuli ufp4, xmmh, ufp2, srcSize=2, destSize=4, ext=(0x2 | 0x10) + mmuli ufp3, xmmh, ufp2, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 0x20" + mmuli ufp4, xmmh, ufp2, srcSize=2, destSize=4, ext = Signed + "| 0x10" maddi xmmh, ufp3, ufp4, size=4, ext=0 }; @@ -78,11 +78,11 @@ def macroop PMADDWD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - mmuli ufp3, xmml, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20) - mmuli ufp4, xmml, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10) + mmuli ufp3, xmml, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 0x20" + mmuli ufp4, xmml, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10" maddi xmml, ufp3, ufp4, size=4, ext=0 - mmuli ufp3, xmmh, ufp2, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20) - mmuli ufp4, xmmh, ufp2, srcSize=2, destSize=4, ext=(0x2 | 0x10) + mmuli ufp3, xmmh, ufp2, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 0x20" + mmuli ufp4, xmmh, ufp2, srcSize=2, destSize=4, ext = Signed + "| 0x10" maddi xmmh, ufp3, ufp4, size=4, ext=0 }; ''' diff --git a/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py b/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py index fdfb08667..d73434832 100644 --- a/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py +++ b/src/arch/x86/isa/insts/simd128/integer/arithmetic/subtraction.py @@ -135,43 +135,43 @@ def macroop PSUBQ_XMM_P { }; def macroop PSUBSB_XMM_XMM { - msubi xmml, xmml, xmmlm, size=1, ext=4 - msubi xmmh, xmmh, xmmhm, size=1, ext=4 + msubi xmml, xmml, xmmlm, size=1, ext = "2 |" + Signed + msubi xmmh, xmmh, xmmhm, size=1, ext = "2 |" + Signed }; def macroop PSUBSB_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - msubi xmml, xmml, ufp1, size=1, ext=4 - msubi xmmh, xmmh, ufp2, size=1, ext=4 + msubi xmml, xmml, ufp1, size=1, ext = "2 |" + Signed + msubi xmmh, xmmh, ufp2, size=1, ext = "2 |" + Signed }; def macroop PSUBSB_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - msubi xmml, xmml, ufp1, size=1, ext=4 - msubi xmmh, xmmh, ufp2, size=1, ext=4 + msubi xmml, xmml, ufp1, size=1, ext = "2 |" + Signed + msubi xmmh, xmmh, ufp2, size=1, ext = "2 |" + Signed }; def macroop PSUBSW_XMM_XMM { - msubi xmml, xmml, xmmlm, size=2, ext=4 - msubi xmmh, xmmh, xmmhm, size=2, ext=4 + msubi xmml, xmml, xmmlm, size=2, ext = "2 |" + Signed + msubi xmmh, xmmh, xmmhm, size=2, ext = "2 |" + Signed }; def macroop PSUBSW_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - msubi xmml, xmml, ufp1, size=2, ext=4 - msubi xmmh, xmmh, ufp2, size=2, ext=4 + msubi xmml, xmml, ufp1, size=2, ext = "2 |" + Signed + msubi xmmh, xmmh, ufp2, size=2, ext = "2 |" + Signed }; def macroop PSUBSW_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - msubi xmml, xmml, ufp1, size=2, ext=4 - msubi xmmh, xmmh, ufp2, size=2, ext=4 + msubi xmml, xmml, ufp1, size=2, ext = "2 |" + Signed + msubi xmmh, xmmh, ufp2, size=2, ext = "2 |" + Signed }; def macroop PSUBUSB_XMM_XMM { diff --git a/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py b/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py index d3bfbb529..6610e0690 100644 --- a/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py +++ b/src/arch/x86/isa/insts/simd128/integer/compare/compare_and_write_minimum_or_maximum.py @@ -75,23 +75,23 @@ def macroop PMINUB_XMM_P { }; def macroop PMINSW_XMM_XMM { - mmini xmml, xmml, xmmlm, size=2, ext=2 - mmini xmmh, xmmh, xmmhm, size=2, ext=2 + mmini xmml, xmml, xmmlm, size=2, ext=Signed + mmini xmmh, xmmh, xmmhm, size=2, ext=Signed }; def macroop PMINSW_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - mmini xmml, xmml, ufp1, size=2, ext=2 - mmini xmmh, xmmh, ufp2, size=2, ext=2 + mmini xmml, xmml, ufp1, size=2, ext=Signed + mmini xmmh, xmmh, ufp2, size=2, ext=Signed }; def macroop PMINSW_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - mmini xmml, xmml, ufp1, size=2, ext=2 - mmini xmmh, xmmh, ufp2, size=2, ext=2 + mmini xmml, xmml, ufp1, size=2, ext=Signed + mmini xmmh, xmmh, ufp2, size=2, ext=Signed }; def macroop PMAXUB_XMM_XMM { @@ -115,22 +115,22 @@ def macroop PMAXUB_XMM_P { }; def macroop PMAXSW_XMM_XMM { - mmaxi xmml, xmml, xmmlm, size=2, ext=2 - mmaxi xmmh, xmmh, xmmhm, size=2, ext=2 + mmaxi xmml, xmml, xmmlm, size=2, ext=Signed + mmaxi xmmh, xmmh, xmmhm, size=2, ext=Signed }; def macroop PMAXSW_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - mmaxi xmml, xmml, ufp1, size=2, ext=2 - mmaxi xmmh, xmmh, ufp2, size=2, ext=2 + mmaxi xmml, xmml, ufp1, size=2, ext=Signed + mmaxi xmmh, xmmh, ufp2, size=2, ext=Signed }; def macroop PMAXSW_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - mmaxi xmml, xmml, ufp1, size=2, ext=2 - mmaxi xmmh, xmmh, ufp2, size=2, ext=2 + mmaxi xmml, xmml, ufp1, size=2, ext=Signed + mmaxi xmmh, xmmh, ufp2, size=2, ext=Signed }; ''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py index 8d632a0ac..080be66f6 100644 --- a/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py +++ b/src/arch/x86/isa/insts/simd128/integer/data_conversion/convert_gpr_integer_to_floating_point.py @@ -56,33 +56,33 @@ microcode = ''' def macroop CVTSI2SS_XMM_R { mov2fp ufp1, regm, destSize=dsz, srcSize=dsz - cvti2f xmml, ufp1, srcSize=dsz, destSize=4, ext=1 + cvti2f xmml, ufp1, srcSize=dsz, destSize=4, ext=Scalar }; def macroop CVTSI2SS_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - cvti2f xmml, ufp1, srcSize=dsz, destSize=4, ext=1 + cvti2f xmml, ufp1, srcSize=dsz, destSize=4, ext=Scalar }; def macroop CVTSI2SS_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - cvti2f xmml, ufp1, srcSize=dsz, destSize=4, ext=1 + cvti2f xmml, ufp1, srcSize=dsz, destSize=4, ext=Scalar }; def macroop CVTSI2SD_XMM_R { mov2fp ufp1, regm, destSize=dsz, srcSize=dsz - cvti2f xmml, ufp1, srcSize=dsz, destSize=8, ext=1 + cvti2f xmml, ufp1, srcSize=dsz, destSize=8, ext=Scalar }; def macroop CVTSI2SD_XMM_M { ldfp ufp1, seg, sib, disp, dataSize=8 - cvti2f xmml, ufp1, srcSize=dsz, destSize=8, ext=1 + cvti2f xmml, ufp1, srcSize=dsz, destSize=8, ext=Scalar }; def macroop CVTSI2SD_XMM_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - cvti2f xmml, ufp1, srcSize=dsz, destSize=8, ext=1 + cvti2f xmml, ufp1, srcSize=dsz, destSize=8, ext=Scalar }; ''' diff --git a/src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py b/src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py index 9112a7382..7afee6cbf 100644 --- a/src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py +++ b/src/arch/x86/isa/insts/simd128/integer/data_reordering/pack_with_saturation.py @@ -55,45 +55,45 @@ microcode = ''' def macroop PACKSSDW_XMM_XMM { - pack ufp1, xmml, xmmh, ext=1, srcSize=4, destSize=2 - pack xmmh, xmmlm, xmmhm, ext=1, srcSize=4, destSize=2 + pack ufp1, xmml, xmmh, ext=Signed, srcSize=4, destSize=2 + pack xmmh, xmmlm, xmmhm, ext=Signed, srcSize=4, destSize=2 movfp xmml, ufp1, dataSize=8 }; def macroop PACKSSDW_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - pack xmml, xmml, xmmh, ext=1, srcSize=4, destSize=2 - pack xmmh, ufp1, ufp2, ext=1, srcSize=4, destSize=2 + pack xmml, xmml, xmmh, ext=Signed, srcSize=4, destSize=2 + pack xmmh, ufp1, ufp2, ext=Signed, srcSize=4, destSize=2 }; def macroop PACKSSDW_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - pack xmml, xmml, xmmh, ext=1, srcSize=4, destSize=2 - pack xmmh, ufp1, ufp2, ext=1, srcSize=4, destSize=2 + pack xmml, xmml, xmmh, ext=Signed, srcSize=4, destSize=2 + pack xmmh, ufp1, ufp2, ext=Signed, srcSize=4, destSize=2 }; def macroop PACKSSWB_XMM_XMM { - pack ufp1, xmml, xmmh, ext=1, srcSize=2, destSize=1 - pack xmmh, xmmlm, xmmhm, ext=1, srcSize=2, destSize=1 + pack ufp1, xmml, xmmh, ext=Signed, srcSize=2, destSize=1 + pack xmmh, xmmlm, xmmhm, ext=Signed, srcSize=2, destSize=1 movfp xmml, ufp1, dataSize=8 }; def macroop PACKSSWB_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - pack xmml, xmml, xmmh, ext=1, srcSize=2, destSize=1 - pack xmmh, ufp1, ufp2, ext=1, srcSize=2, destSize=1 + pack xmml, xmml, xmmh, ext=Signed, srcSize=2, destSize=1 + pack xmmh, ufp1, ufp2, ext=Signed, srcSize=2, destSize=1 }; def macroop PACKSSWB_XMM_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, riprel, "DISPLACEMENT + 8", dataSize=8 - pack xmml, xmml, xmmh, ext=1, srcSize=2, destSize=1 - pack xmmh, ufp1, ufp2, ext=1, srcSize=2, destSize=1 + pack xmml, xmml, xmmh, ext=Signed, srcSize=2, destSize=1 + pack xmmh, ufp1, ufp2, ext=Signed, srcSize=2, destSize=1 }; def macroop PACKUSWB_XMM_XMM { @@ -105,8 +105,8 @@ def macroop PACKUSWB_XMM_XMM { def macroop PACKUSWB_XMM_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 ldfp ufp2, seg, sib, "DISPLACEMENT + 8", dataSize=8 - pack xmml, xmml, xmmh, ext=0, srcSize=2, destSize=1 - pack xmmh, ufp1, ufp2, ext=0, srcSize=2, destSize=1 + pack xmml, xmml, xmmh, ext=Signed, srcSize=2, destSize=1 + pack xmmh, ufp1, ufp2, ext=Signed, srcSize=2, destSize=1 }; def macroop PACKUSWB_XMM_P { diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/addition.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/addition.py index b663d15b7..d376dccce 100644 --- a/src/arch/x86/isa/insts/simd64/integer/arithmetic/addition.py +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/addition.py @@ -115,33 +115,33 @@ def macroop PADDQ_MMX_P { }; def macroop PADDSB_MMX_MMX { - maddi mmx, mmx, mmxm, size=1, ext=4 + maddi mmx, mmx, mmxm, size=1, ext = "2 |" + Signed }; def macroop PADDSB_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - maddi mmx, mmx, ufp1, size=1, ext=4 + maddi mmx, mmx, ufp1, size=1, ext = "2 |" + Signed }; def macroop PADDSB_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - maddi mmx, mmx, ufp1, size=1, ext=4 + maddi mmx, mmx, ufp1, size=1, ext = "2 |" + Signed }; def macroop PADDSW_MMX_MMX { - maddi mmx, mmx, mmxm, size=2, ext=4 + maddi mmx, mmx, mmxm, size=2, ext = "2 |" + Signed }; def macroop PADDSW_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - maddi mmx, mmx, ufp1, size=2, ext=4 + maddi mmx, mmx, ufp1, size=2, ext = "2 |" + Signed }; def macroop PADDSW_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - maddi mmx, mmx, ufp1, size=2, ext=4 + maddi mmx, mmx, ufp1, size=2, ext = "2 |" + Signed }; def macroop PADDUSB_MMX_MMX { diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py index 7383a744f..526162e32 100644 --- a/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiplication.py @@ -55,77 +55,77 @@ microcode = ''' def macroop PMULHW_MMX_MMX { - mmuli mmx, mmx, mmxm, size=2, ext=(0x2 | 0x8) + mmuli mmx, mmx, mmxm, size=2, ext = Signed + "|" + MultHi }; def macroop PMULHW_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mmuli mmx, mmx, ufp1, size=2, ext=(0x2 | 0x8) + mmuli mmx, mmx, ufp1, size=2, ext = Signed + "|" + MultHi }; def macroop PMULHW_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mmuli mmx, mmx, ufp1, size=2, ext=(0x2 | 0x8) + mmuli mmx, mmx, ufp1, size=2, ext = Signed + "|" + MultHi }; def macroop PMULLW_MMX_MMX { - mmuli mmx, mmx, mmxm, size=2, ext=2 + mmuli mmx, mmx, mmxm, size=2, ext = Signed }; def macroop PMULLW_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mmuli mmx, mmx, ufp1, size=2, ext=2 + mmuli mmx, mmx, ufp1, size=2, ext = Signed }; def macroop PMULLW_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mmuli mmx, mmx, ufp1, size=2, ext=2 + mmuli mmx, mmx, ufp1, size=2, ext = Signed }; def macroop PMULHRW_MMX_MMX { - mmuli mmx, mmx, mmxm, size=2, ext=(0x2 | 0x4 | 0x8) + mmuli mmx, mmx, mmxm, size=2, ext = Signed + "| 0x4 |" + MultHi }; def macroop PMULHRW_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mmuli mmx, mmx, ufp1, size=2, ext=(0x2 | 0x4 | 0x8) + mmuli mmx, mmx, ufp1, size=2, ext = Signed + "| 0x4 |" + MultHi }; def macroop PMULHRW_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mmuli mmx, mmx, ufp1, size=2, ext=(0x2 | 0x4 | 0x8) + mmuli mmx, mmx, ufp1, size=2, ext = Signed + "| 0x4 |" + MultHi }; def macroop PMULHUW_MMX_MMX { - mmuli mmx, mmx, mmxm, size=2, ext=8 + mmuli mmx, mmx, mmxm, size=2, ext = MultHi }; def macroop PMULHUW_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mmuli mmx, mmx, ufp1, size=2, ext=8 + mmuli mmx, mmx, ufp1, size=2, ext = MultHi }; def macroop PMULHUW_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mmuli mmx, mmx, ufp1, size=2, ext=8 + mmuli mmx, mmx, ufp1, size=2, ext = MultHi }; def macroop PMULUDQ_MMX_MMX { - mmuli mmx, mmx, mmxm, srcSize=4, destSize=8, ext=1 + mmuli mmx, mmx, mmxm, srcSize=4, destSize=8, ext=Scalar }; def macroop PMULUDQ_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mmuli mmx, mmx, ufp1, srcSize=4, destSize=8, ext=1 + mmuli mmx, mmx, ufp1, srcSize=4, destSize=8, ext=Scalar }; def macroop PMULUDQ_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mmuli mmx, mmx, ufp1, srcSize=4, destSize=8, ext=1 + mmuli mmx, mmx, ufp1, srcSize=4, destSize=8, ext=Scalar }; ''' diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiply_add.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiply_add.py index f6940d159..354cf8722 100644 --- a/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiply_add.py +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/multiply_add.py @@ -55,23 +55,23 @@ microcode = ''' def macroop PMADDWD_MMX_MMX { - mmuli ufp3, mmx, mmxm, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20) - mmuli ufp4, mmx, mmxm, srcSize=2, destSize=4, ext=(0x2 | 0x10) + mmuli ufp3, mmx, mmxm, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 0x20" + mmuli ufp4, mmx, mmxm, srcSize=2, destSize=4, ext = Signed + "| 0x10" maddi mmx, ufp3, ufp4, size=4, ext=0 }; def macroop PMADDWD_MMX_M { ldfp ufp1, seg, sib, "DISPLACEMENT", dataSize=8 - mmuli ufp3, mmx, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20) - mmuli ufp4, mmx, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10) + mmuli ufp3, mmx, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 0x20" + mmuli ufp4, mmx, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10" maddi mmx, ufp3, ufp4, size=4, ext=0 }; def macroop PMADDWD_MMX_P { rdip t7 ldfp ufp1, seg, riprel, "DISPLACEMENT", dataSize=8 - mmuli ufp3, mmx, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10 | 0x20) - mmuli ufp4, mmx, ufp1, srcSize=2, destSize=4, ext=(0x2 | 0x10) + mmuli ufp3, mmx, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10 | 0x20" + mmuli ufp4, mmx, ufp1, srcSize=2, destSize=4, ext = Signed + "| 0x10" maddi mmx, ufp3, ufp4, size=4, ext=0 }; ''' diff --git a/src/arch/x86/isa/insts/simd64/integer/arithmetic/subtraction.py b/src/arch/x86/isa/insts/simd64/integer/arithmetic/subtraction.py index a60c0b1a8..4ee87e0f8 100644 --- a/src/arch/x86/isa/insts/simd64/integer/arithmetic/subtraction.py +++ b/src/arch/x86/isa/insts/simd64/integer/arithmetic/subtraction.py @@ -115,33 +115,33 @@ def macroop PSUBQ_MMX_P { }; def macroop PSUBSB_MMX_MMX { - msubi mmx, mmx, mmxm, size=1, ext=4 + msubi mmx, mmx, mmxm, size=1, ext = "2 |" + Signed }; def macroop PSUBSB_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - msubi mmx, mmx, ufp1, size=1, ext=4 + msubi mmx, mmx, ufp1, size=1, ext = "2 |" + Signed }; def macroop PSUBSB_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - msubi mmx, mmx, ufp1, size=1, ext=4 + msubi mmx, mmx, ufp1, size=1, ext = "2 |" + Signed }; def macroop PSUBSW_MMX_MMX { - msubi mmx, mmx, mmxm, size=2, ext=4 + msubi mmx, mmx, mmxm, size=2, ext = "2 |" + Signed }; def macroop PSUBSW_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - msubi mmx, mmx, ufp1, size=2, ext=4 + msubi mmx, mmx, ufp1, size=2, ext = "2 |" + Signed }; def macroop PSUBSW_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - msubi mmx, mmx, ufp1, size=2, ext=4 + msubi mmx, mmx, ufp1, size=2, ext = "2 |" + Signed }; def macroop PSUBUSB_MMX_MMX { diff --git a/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_minimum_or_maximum.py b/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_minimum_or_maximum.py index 8d8247300..c2eedbb0e 100644 --- a/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_minimum_or_maximum.py +++ b/src/arch/x86/isa/insts/simd64/integer/compare/compare_and_write_minimum_or_maximum.py @@ -70,18 +70,18 @@ def macroop PMINUB_MMX_P { }; def macroop PMINSW_MMX_MMX { - mmini mmx, mmx, mmxm, size=2, ext=2 + mmini mmx, mmx, mmxm, size=2, ext=Signed }; def macroop PMINSW_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mmini mmx, mmx, ufp1, size=2, ext=2 + mmini mmx, mmx, ufp1, size=2, ext=Signed }; def macroop PMINSW_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mmini mmx, mmx, ufp1, size=2, ext=2 + mmini mmx, mmx, ufp1, size=2, ext=Signed }; def macroop PMAXUB_MMX_MMX { @@ -100,17 +100,17 @@ def macroop PMAXUB_MMX_P { }; def macroop PMAXSW_MMX_MMX { - mmaxi mmx, mmx, mmxm, size=2, ext=2 + mmaxi mmx, mmx, mmxm, size=2, ext=Signed }; def macroop PMAXSW_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - mmaxi mmx, mmx, ufp1, size=2, ext=2 + mmaxi mmx, mmx, ufp1, size=2, ext=Signed }; def macroop PMAXSW_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - mmaxi mmx, mmx, ufp1, size=2, ext=2 + mmaxi mmx, mmx, ufp1, size=2, ext=Signed }; ''' diff --git a/src/arch/x86/isa/insts/simd64/integer/data_reordering/pack_with_saturation.py b/src/arch/x86/isa/insts/simd64/integer/data_reordering/pack_with_saturation.py index 4235d7f26..cb8b4eaa7 100644 --- a/src/arch/x86/isa/insts/simd64/integer/data_reordering/pack_with_saturation.py +++ b/src/arch/x86/isa/insts/simd64/integer/data_reordering/pack_with_saturation.py @@ -55,33 +55,33 @@ microcode = ''' def macroop PACKSSDW_MMX_MMX { - pack mmx, mmx, mmxm, ext=1, srcSize=4, destSize=2 + pack mmx, mmx, mmxm, ext=Signed, srcSize=4, destSize=2 }; def macroop PACKSSDW_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - pack mmx, mmx, ufp1, ext=1, srcSize=4, destSize=2 + pack mmx, mmx, ufp1, ext=Signed, srcSize=4, destSize=2 }; def macroop PACKSSDW_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - pack mmx, mmx, ufp1, ext=1, srcSize=4, destSize=2 + pack mmx, mmx, ufp1, ext=Signed, srcSize=4, destSize=2 }; def macroop PACKSSWB_MMX_MMX { - pack mmx, mmx, mmxm, ext=1, srcSize=2, destSize=1 + pack mmx, mmx, mmxm, ext=Signed, srcSize=2, destSize=1 }; def macroop PACKSSWB_MMX_M { ldfp ufp1, seg, sib, disp, dataSize=8 - pack mmx, mmx, ufp1, ext=1, srcSize=2, destSize=1 + pack mmx, mmx, ufp1, ext=Signed, srcSize=2, destSize=1 }; def macroop PACKSSWB_MMX_P { rdip t7 ldfp ufp1, seg, riprel, disp, dataSize=8 - pack mmx, mmx, ufp1, ext=1, srcSize=2, destSize=1 + pack mmx, mmx, ufp1, ext=Signed, srcSize=2, destSize=1 }; def macroop PACKUSWB_MMX_MMX { diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa index 25b58dfb7..b0b557521 100644 --- a/src/arch/x86/isa/microasm.isa +++ b/src/arch/x86/isa/microasm.isa @@ -181,6 +181,9 @@ let {{ 'kernel_gs_base'): assembler.symbols[reg] = regIdx("MISCREG_%s" % reg.upper()) + for flag in ('Scalar', 'MultHi', 'Signed'): + assembler.symbols[flag] = 'Media%sOp' % flag + # Code literal which forces a default 64 bit operand size in 64 bit mode. assembler.symbols["oszIn64Override"] = ''' if (machInst.mode.submode == SixtyFourBitMode && diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 4052f254d..900c166f8 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -352,7 +352,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -451,14 +451,14 @@ let {{ // Handle saturation. if (signBit) { if (overflow != mask(destBits - srcBits + 1)) { - if (ext & 0x1) + if (signedOp()) picked = (ULL(1) << (destBits - 1)); else picked = 0; } } else { if (overflow != 0) { - if (ext & 0x1) + if (signedOp()) picked = mask(destBits - 1); else picked = mask(destBits); @@ -479,14 +479,14 @@ let {{ // Handle saturation. if (signBit) { if (overflow != mask(destBits - srcBits + 1)) { - if (ext & 0x1) + if (signedOp()) picked = (ULL(1) << (destBits - 1)); else picked = 0; } } else { if (overflow != 0) { - if (ext & 0x1) + if (signedOp()) picked = mask(destBits - 1); else picked = mask(destBits); @@ -545,7 +545,7 @@ let {{ int size = srcSize; int sizeBits = size * 8; assert(srcSize == 4 || srcSize == 8); - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -595,7 +595,7 @@ let {{ int size = srcSize; int sizeBits = size * 8; assert(srcSize == 4 || srcSize == 8); - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -634,7 +634,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -648,7 +648,7 @@ let {{ (0 - (arg2Bits & (ULL(1) << (sizeBits - 1)))); uint64_t resBits; - if (ext & 0x2) { + if (signedOp()) { if (arg1 < arg2) { resBits = arg1Bits; } else { @@ -672,7 +672,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -686,7 +686,7 @@ let {{ (0 - (arg2Bits & (ULL(1) << (sizeBits - 1)))); uint64_t resBits; - if (ext & 0x2) { + if (signedOp()) { if (arg1 > arg2) { resBits = arg1Bits; } else { @@ -725,7 +725,7 @@ let {{ int size = srcSize; int sizeBits = size * 8; assert(srcSize == 4 || srcSize == 8); - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -766,7 +766,7 @@ let {{ int size = srcSize; int sizeBits = size * 8; assert(srcSize == 4 || srcSize == 8); - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -812,7 +812,7 @@ let {{ int size = srcSize; int sizeBits = size * 8; assert(srcSize == 4 || srcSize == 8); - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -858,7 +858,7 @@ let {{ int size = srcSize; int sizeBits = size * 8; assert(srcSize == 4 || srcSize == 8); - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -904,7 +904,7 @@ let {{ int size = srcSize; int sizeBits = size * 8; assert(srcSize == 4 || srcSize == 8); - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -938,7 +938,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -949,17 +949,19 @@ let {{ uint64_t resBits = arg1Bits + arg2Bits; if (ext & 0x2) { - if (findCarry(sizeBits, resBits, arg1Bits, arg2Bits)) - resBits = mask(sizeBits); - } else if (ext & 0x4) { - int arg1Sign = bits(arg1Bits, sizeBits - 1); - int arg2Sign = bits(arg2Bits, sizeBits - 1); - int resSign = bits(resBits, sizeBits - 1); - if ((arg1Sign == arg2Sign) && (arg1Sign != resSign)) { - if (resSign == 0) - resBits = (ULL(1) << (sizeBits - 1)); - else - resBits = mask(sizeBits - 1); + if (signedOp()) { + int arg1Sign = bits(arg1Bits, sizeBits - 1); + int arg2Sign = bits(arg2Bits, sizeBits - 1); + int resSign = bits(resBits, sizeBits - 1); + if ((arg1Sign == arg2Sign) && (arg1Sign != resSign)) { + if (resSign == 0) + resBits = (ULL(1) << (sizeBits - 1)); + else + resBits = mask(sizeBits - 1); + } + } else { + if (findCarry(sizeBits, resBits, arg1Bits, arg2Bits)) + resBits = mask(sizeBits); } } @@ -973,7 +975,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -984,21 +986,23 @@ let {{ uint64_t resBits = arg1Bits - arg2Bits; if (ext & 0x2) { - if (arg2Bits > arg1Bits) { - resBits = 0; - } else if (!findCarry(sizeBits, resBits, - arg1Bits, ~arg2Bits)) { - resBits = mask(sizeBits); - } - } else if (ext & 0x4) { - int arg1Sign = bits(arg1Bits, sizeBits - 1); - int arg2Sign = !bits(arg2Bits, sizeBits - 1); - int resSign = bits(resBits, sizeBits - 1); - if ((arg1Sign == arg2Sign) && (arg1Sign != resSign)) { - if (resSign == 0) - resBits = (ULL(1) << (sizeBits - 1)); - else - resBits = mask(sizeBits - 1); + if (signedOp()) { + int arg1Sign = bits(arg1Bits, sizeBits - 1); + int arg2Sign = !bits(arg2Bits, sizeBits - 1); + int resSign = bits(resBits, sizeBits - 1); + if ((arg1Sign == arg2Sign) && (arg1Sign != resSign)) { + if (resSign == 0) + resBits = (ULL(1) << (sizeBits - 1)); + else + resBits = mask(sizeBits - 1); + } + } else { + if (arg2Bits > arg1Bits) { + resBits = 0; + } else if (!findCarry(sizeBits, resBits, + arg1Bits, ~arg2Bits)) { + resBits = mask(sizeBits); + } } } @@ -1013,7 +1017,7 @@ let {{ int destBits = destSize * 8; assert(destBits <= 64); assert(destSize >= srcSize); - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / destSize); + int items = numItems(destSize); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -1030,7 +1034,7 @@ let {{ uint64_t arg2Bits = bits(FpSrcReg2.uqw, srcHiIndex, srcLoIndex); uint64_t resBits; - if (ext & 0x2) { + if (signedOp()) { int64_t arg1 = arg1Bits | (0 - (arg1Bits & (ULL(1) << (srcBits - 1)))); int64_t arg2 = arg2Bits | @@ -1043,7 +1047,7 @@ let {{ if (ext & 0x4) resBits += (ULL(1) << (destBits - 1)); - if (ext & 0x8) + if (multHi()) resBits >>= destBits; int destHiIndex = (i + 1) * destBits - 1; @@ -1058,7 +1062,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -1098,7 +1102,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t shiftAmt = op2.uqw; uint64_t result = FpDestReg.uqw; @@ -1125,7 +1129,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t shiftAmt = op2.uqw; uint64_t result = FpDestReg.uqw; @@ -1156,7 +1160,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t shiftAmt = op2.uqw; uint64_t result = FpDestReg.uqw; @@ -1201,15 +1205,15 @@ let {{ int srcStart = 0; int destStart = 0; if (srcSize == 2 * destSize) { - items = (ext & 0x1) ? 1: sizeof(FloatRegBits) / srcSize; + items = numItems(srcSize); if (ext & 0x2) destStart = destSizeBits * items; } else if (destSize == 2 * srcSize) { - items = (ext & 0x1) ? 1: sizeof(FloatRegBits) / destSize; + items = numItems(destSize); if (ext & 0x2) srcStart = srcSizeBits * items; } else { - items = (ext & 0x1) ? 1: sizeof(FloatRegBits) / destSize; + items = numItems(destSize); } uint64_t result = FpDestReg.uqw; @@ -1273,15 +1277,15 @@ let {{ int srcStart = 0; int destStart = 0; if (srcSize == 2 * destSize) { - items = (ext & 0x1) ? 1: sizeof(FloatRegBits) / srcSize; + items = numItems(srcSize); if (ext & 0x2) destStart = destSizeBits * items; } else if (destSize == 2 * srcSize) { - items = (ext & 0x1) ? 1: sizeof(FloatRegBits) / destSize; + items = numItems(destSize); if (ext & 0x2) srcStart = srcSizeBits * items; } else { - items = (ext & 0x1) ? 1: sizeof(FloatRegBits) / destSize; + items = numItems(destSize); } uint64_t result = FpDestReg.uqw; @@ -1334,15 +1338,15 @@ let {{ int srcStart = 0; int destStart = 0; if (srcSize == 2 * destSize) { - items = (ext & 0x1) ? 1: sizeof(FloatRegBits) / srcSize; + items = numItems(srcSize); if (ext & 0x2) destStart = destSizeBits * items; } else if (destSize == 2 * srcSize) { - items = (ext & 0x1) ? 1: sizeof(FloatRegBits) / destSize; + items = numItems(destSize); if (ext & 0x2) srcStart = srcSizeBits * items; } else { - items = (ext & 0x1) ? 1: sizeof(FloatRegBits) / destSize; + items = numItems(destSize); } uint64_t result = FpDestReg.uqw; @@ -1393,7 +1397,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x1) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { @@ -1432,7 +1436,7 @@ let {{ assert(srcSize == destSize); int size = srcSize; int sizeBits = size * 8; - int items = (ext & 0x8) ? 1: (sizeof(FloatRegBits) / size); + int items = numItems(size); uint64_t result = FpDestReg.uqw; for (int i = 0; i < items; i++) { diff --git a/src/cpu/base.hh b/src/cpu/base.hh index bfeec0870..b229ddd38 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -274,7 +274,7 @@ class BaseCPU : public MemObject */ virtual BranchPred *getBranchPred() { return NULL; }; - virtual Counter totalInstructions() const { return 0; } + virtual Counter totalInstructions() const = 0; // Function tracing private: diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py index 5476becc6..d4ab2cb17 100644 --- a/src/dev/x86/I82094AA.py +++ b/src/dev/x86/I82094AA.py @@ -38,6 +38,8 @@ class I82094AA(BasicPioDevice): pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") pio_addr = Param.Addr("Device address") int_port = Port("Port for sending and receiving interrupt messages") + int_latency = Param.Latency('1ns', \ + "Latency for an interrupt to propagate through this device.") external_int_pic = Param.I8259(NULL, "External PIC, if any") def pin(self, line): diff --git a/src/dev/x86/i82094aa.cc b/src/dev/x86/i82094aa.cc index 591fee6a4..65b3ee732 100644 --- a/src/dev/x86/i82094aa.cc +++ b/src/dev/x86/i82094aa.cc @@ -36,7 +36,8 @@ #include "mem/packet_access.hh" #include "sim/system.hh" -X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this), +X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), + IntDev(this, p->int_latency), latency(p->pio_latency), pioAddr(p->pio_addr), extIntPic(p->external_int_pic), lowestPriorityOffset(0) { diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 429928c79..2397a17c5 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -266,7 +266,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, return false; } - blk = tags->accessBlock(pkt->getAddr(), lat); + int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + blk = tags->accessBlock(pkt->getAddr(), lat, id); DPRINTF(Cache, "%s%s %x %s\n", pkt->cmdString(), pkt->req->isInstFetch() ? " (ifetch)" : "", @@ -299,7 +300,8 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, incMissCount(pkt); return false; } - tags->insertBlock(pkt->getAddr(), blk); + int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + tags->insertBlock(pkt->getAddr(), blk, id); blk->status = BlkValid | BlkReadable; } std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize); @@ -976,7 +978,8 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk, tempBlock->tag = tags->extractTag(addr); DPRINTF(Cache, "using temp block for %x\n", addr); } else { - tags->insertBlock(addr, blk); + int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + tags->insertBlock(pkt->getAddr(), blk, id); } } else { // existing block... probably an upgrade diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc index 122e6e14b..808f9e25a 100644 --- a/src/mem/cache/tags/fa_lru.cc +++ b/src/mem/cache/tags/fa_lru.cc @@ -154,7 +154,7 @@ FALRU::invalidateBlk(FALRU::BlkType *blk) } FALRUBlk* -FALRU::accessBlock(Addr addr, int &lat, int *inCache) +FALRU::accessBlock(Addr addr, int &lat, int context_src, int *inCache) { accesses++; int tmp_in_cache = 0; @@ -228,7 +228,7 @@ FALRU::findVictim(Addr addr, PacketList &writebacks) } void -FALRU::insertBlock(Addr addr, FALRU::BlkType *blk) +FALRU::insertBlock(Addr addr, FALRU::BlkType *blk, int context_src) { } diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index 4e6bccc1d..b20d25d2b 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -182,7 +182,7 @@ public: * @param inCache The FALRUBlk::inCache flags. * @return Pointer to the cache block. */ - FALRUBlk* accessBlock(Addr addr, int &lat, int *inCache = 0); + FALRUBlk* accessBlock(Addr addr, int &lat, int context_src, int *inCache = 0); /** * Find the block in the cache, do not update the replacement data. @@ -200,7 +200,7 @@ public: */ FALRUBlk* findVictim(Addr addr, PacketList & writebacks); - void insertBlock(Addr addr, BlkType *blk); + void insertBlock(Addr addr, BlkType *blk, int context_src); /** * Return the hit latency of this cache. diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc index b9ba5256b..a8ef4e6fb 100644 --- a/src/mem/cache/tags/iic.cc +++ b/src/mem/cache/tags/iic.cc @@ -219,7 +219,7 @@ IIC::regStats(const string &name) IICTag* -IIC::accessBlock(Addr addr, int &lat) +IIC::accessBlock(Addr addr, int &lat, int context_src) { Addr tag = extractTag(addr); unsigned set = hash(addr); @@ -338,7 +338,7 @@ IIC::findVictim(Addr addr, PacketList &writebacks) } void -IIC::insertBlock(Addr addr, BlkType* blk) +IIC::insertBlock(Addr addr, BlkType* blk, int context_src) { } diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh index 994f7b8f7..c96cdaf3e 100644 --- a/src/mem/cache/tags/iic.hh +++ b/src/mem/cache/tags/iic.hh @@ -422,7 +422,7 @@ class IIC : public BaseTags * @param lat The access latency. * @return A pointer to the block found, if any. */ - IICTag* accessBlock(Addr addr, int &lat); + IICTag* accessBlock(Addr addr, int &lat, int context_src); /** * Find the block, do not update the replacement data. @@ -440,7 +440,7 @@ class IIC : public BaseTags */ IICTag* findVictim(Addr addr, PacketList &writebacks); - void insertBlock(Addr addr, BlkType *blk); + void insertBlock(Addr addr, BlkType *blk, int context_src); /** * Called at end of simulation to complete average block reference stats. diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc index 9371f193a..81d82c231 100644 --- a/src/mem/cache/tags/lru.cc +++ b/src/mem/cache/tags/lru.cc @@ -150,7 +150,7 @@ LRU::~LRU() } LRUBlk* -LRU::accessBlock(Addr addr, int &lat) +LRU::accessBlock(Addr addr, int &lat, int context_src) { Addr tag = extractTag(addr); unsigned set = extractSet(addr); @@ -200,7 +200,7 @@ LRU::findVictim(Addr addr, PacketList &writebacks) } void -LRU::insertBlock(Addr addr, LRU::BlkType *blk) +LRU::insertBlock(Addr addr, LRU::BlkType *blk, int context_src) { if (!blk->isTouched) { tagsInUse++; diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh index 2874d8f1f..ecd6e861f 100644 --- a/src/mem/cache/tags/lru.hh +++ b/src/mem/cache/tags/lru.hh @@ -172,7 +172,7 @@ public: * @param lat The access latency. * @return Pointer to the cache block if found. */ - LRUBlk* accessBlock(Addr addr, int &lat); + LRUBlk* accessBlock(Addr addr, int &lat, int context_src); /** * Finds the given address in the cache, do not update replacement data. @@ -197,7 +197,7 @@ public: * @param addr The address to update. * @param blk The block to update. */ - void insertBlock(Addr addr, BlkType *blk); + void insertBlock(Addr addr, BlkType *blk, int context_src); /** * Generate the tag from the given address. diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index 4bc3a4434..bcaf5582a 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -222,6 +222,6 @@ PageTable::unserialize(Checkpoint *cp, const std::string §ion) entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i)); pTable[vaddr] = *entry; ++i; - } + } } diff --git a/src/mem/physical.cc b/src/mem/physical.cc index 121a6e447..081fbb4cb 100644 --- a/src/mem/physical.cc +++ b/src/mem/physical.cc @@ -540,12 +540,8 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string §ion) /* Only copy bytes that are non-zero, so we don't give the VM system hell */ while (curSize < params()->range.size()) { bytesRead = gzread(compressedMem, tempPage, chunkSize); - if (bytesRead != chunkSize && - bytesRead != params()->range.size() - curSize) - fatal("Read failed on physical memory checkpoint file '%s'" - " got %d bytes, expected %d or %d bytes\n", - filename, bytesRead, chunkSize, - params()->range.size() - curSize); + if (bytesRead == 0) + break; assert(bytesRead % sizeof(long) == 0); diff --git a/src/sim/faults.cc b/src/sim/faults.cc index 0fe853785..6149a8335 100644 --- a/src/sim/faults.cc +++ b/src/sim/faults.cc @@ -40,7 +40,7 @@ #if !FULL_SYSTEM void FaultBase::invoke(ThreadContext * tc) { - fatal("fault (%s) detected @ PC %p", name(), tc->readPC()); + panic("fault (%s) detected @ PC %p", name(), tc->readPC()); } #else void FaultBase::invoke(ThreadContext * tc) @@ -54,7 +54,7 @@ void FaultBase::invoke(ThreadContext * tc) void UnimpFault::invoke(ThreadContext * tc) { - fatal("Unimpfault: %s\n", panicStr.c_str()); + panic("Unimpfault: %s\n", panicStr.c_str()); } #if !FULL_SYSTEM diff --git a/src/sim/process.cc b/src/sim/process.cc index 343d2ad5a..957c3cc3e 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -507,6 +507,7 @@ Process::serialize(std::ostream &os) nameOut(os, csprintf("%s.FdMap%d", name(), x)); fd_map[x].serialize(os); } + SERIALIZE_SCALAR(M5_pid); } @@ -528,6 +529,11 @@ Process::unserialize(Checkpoint *cp, const std::string §ion) fd_map[x].unserialize(cp, csprintf("%s.FdMap%d", section, x)); } fix_file_offsets(); + UNSERIALIZE_OPT_SCALAR(M5_pid); + // The above returns a bool so that you could do something if you don't + // find the param in the checkpoint if you wanted to, like set a default + // but in this case we'll just stick with the instantianted value if not + // found. checkpointRestored = true; diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc index 5ae9128e5..0e6d9b254 100644 --- a/src/sim/serialize.cc +++ b/src/sim/serialize.cc @@ -204,6 +204,18 @@ paramIn(Checkpoint *cp, const string §ion, const string &name, T ¶m) } } +template <class T> +bool +optParamIn(Checkpoint *cp, const string §ion, const string &name, T ¶m) +{ + string str; + if (!cp->find(section, name, str) || !parseParam(str, param)) { + warn("optional parameter %s:%s not present\n", section, name); + return false; + } else { + return true; + } +} template <class T> void @@ -322,6 +334,9 @@ paramOut(ostream &os, const string &name, type const ¶m); \ template void \ paramIn(Checkpoint *cp, const string §ion, \ const string &name, type & param); \ +template bool \ +optParamIn(Checkpoint *cp, const string §ion, \ + const string &name, type & param); \ template void \ arrayParamOut(ostream &os, const string &name, \ type const *param, unsigned size); \ @@ -422,7 +437,7 @@ Serializable::serializeAll(const string &cpt_dir) time_t t = time(NULL); if (!outstream.is_open()) fatal("Unable to open file %s for writing\n", cpt_file.c_str()); - outstream << "// checkpoint generated: " << ctime(&t); + outstream << "## checkpoint generated: " << ctime(&t); globals.serialize(outstream); SimObject::serializeAll(outstream); diff --git a/src/sim/serialize.hh b/src/sim/serialize.hh index 08240c0c0..cf1a672be 100644 --- a/src/sim/serialize.hh +++ b/src/sim/serialize.hh @@ -58,6 +58,10 @@ void paramIn(Checkpoint *cp, const std::string §ion, const std::string &name, T ¶m); template <class T> +bool optParamIn(Checkpoint *cp, const std::string §ion, + const std::string &name, T ¶m); + +template <class T> void arrayParamOut(std::ostream &os, const std::string &name, const T *param, unsigned size); @@ -85,6 +89,7 @@ objParamIn(Checkpoint *cp, const std::string §ion, #define SERIALIZE_SCALAR(scalar) paramOut(os, #scalar, scalar) #define UNSERIALIZE_SCALAR(scalar) paramIn(cp, section, #scalar, scalar) +#define UNSERIALIZE_OPT_SCALAR(scalar) optParamIn(cp, section, #scalar, scalar) // ENUMs are like SCALARs, but we cast them to ints on the way out #define SERIALIZE_ENUM(scalar) paramOut(os, #scalar, (int)scalar) |