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-rw-r--r--src/arch/sparc/intregfile.cc7
-rw-r--r--src/arch/sparc/isa/decoder.isa4
-rw-r--r--src/arch/sparc/miscregfile.cc14
-rw-r--r--src/arch/sparc/tlb.cc34
-rw-r--r--src/arch/sparc/ua2005.cc6
-rw-r--r--src/dev/sparc/SConscript1
-rw-r--r--src/dev/sparc/mm_disk.cc137
-rw-r--r--src/dev/sparc/mm_disk.hh70
-rw-r--r--src/python/m5/objects/T1000.py6
9 files changed, 265 insertions, 14 deletions
diff --git a/src/arch/sparc/intregfile.cc b/src/arch/sparc/intregfile.cc
index 0a8ac055f..60856d3fa 100644
--- a/src/arch/sparc/intregfile.cc
+++ b/src/arch/sparc/intregfile.cc
@@ -111,6 +111,8 @@ void IntRegFile::setReg(int intReg, const IntReg &val)
void IntRegFile::setCWP(int cwp)
{
int index = ((NWindows - cwp) % NWindows) * 2;
+ if (index < 0)
+ panic("Index less than 0. cwp=%d nwin=%d\n", cwp, NWindows);
offset[Outputs] = FrameOffset + (index * RegsPerFrame);
offset[Locals] = FrameOffset + ((index+1) * RegsPerFrame);
offset[Inputs] = FrameOffset +
@@ -128,6 +130,11 @@ void IntRegFile::setGlobals(int gl)
regView[Globals] = regGlobals[gl];
offset[Globals] = RegGlobalOffset + gl * RegsPerFrame;
+
+ if (regView[Globals] == regView[Inputs] ||
+ regView[Globals] == regView[Locals] ||
+ regView[Globals] == regView[Outputs] )
+ panic("Two register arrays set to the same thing!\n");
}
void IntRegFile::serialize(std::ostream &os)
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index e2bebd987..2e1344a8f 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -1,4 +1,4 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
@@ -184,7 +184,7 @@ decode OP default Unknown::unknown()
}});
0x0B: smul({{
Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
- Y = Rd.sdw;
+ Y = Rd.sdw<63:32>;
}});
0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
0x0D: udivx({{
diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index c58a1fd09..50f510289 100644
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -326,12 +326,8 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
mbits(tick,63,63);
case MISCREG_FPRS:
- warn("FPRS register read and FPU stuff not really implemented\n");
// in legion if fp is enabled du and dl are set
- if (fprs & 0x4)
- return 0x7;
- else
- return 0;
+ return fprs | 0x3;
case MISCREG_PCR:
case MISCREG_PIC:
panic("Performance Instrumentation not impl\n");
@@ -389,7 +385,6 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
asi = val;
break;
case MISCREG_FPRS:
- warn("FPU not really implemented writing %#X to FPRS\n", val);
fprs = val;
break;
case MISCREG_TICK:
@@ -612,6 +607,8 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val)
void MiscRegFile::setRegWithEffect(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
+ MiscReg new_val = val;
+
switch (miscReg) {
case MISCREG_STICK:
case MISCREG_TICK:
@@ -634,7 +631,8 @@ void MiscRegFile::setRegWithEffect(int miscReg,
tl = val;
return;
case MISCREG_CWP:
- tc->changeRegFileContext(CONTEXT_CWP, val);
+ new_val = val > NWindows ? NWindows - 1 : val;
+ tc->changeRegFileContext(CONTEXT_CWP, new_val);
break;
case MISCREG_GL:
tc->changeRegFileContext(CONTEXT_GLOBALS, val);
@@ -671,7 +669,7 @@ void MiscRegFile::setRegWithEffect(int miscReg,
panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
#endif
}
- setReg(miscReg, val);
+ setReg(miscReg, new_val);
}
void MiscRegFile::serialize(std::ostream & os)
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 40542a9a6..1cecb4ebb 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -625,13 +625,13 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
return new DataAccessException;
}
- } else if (hpriv) {
+ } /*else if (hpriv) {*/
if (asi == ASI_P) {
ct = Primary;
context = pri_context;
goto continueDtbFlow;
}
- }
+ //}
if (!implicit) {
if (AsiIsLittle(asi))
@@ -933,6 +933,36 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
pkt->set(data);
break;
+ case ASI_IMMU_TSB_PS0_PTR_REG:
+ temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+ if (bits(temp,12,0) == 0) {
+ tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
+ cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
+ } else {
+ tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
+ cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
+ }
+ data = mbits(tsbtemp,63,13);
+ data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
+ mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
+ pkt->set(data);
+ break;
+ case ASI_IMMU_TSB_PS1_PTR_REG:
+ temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
+ if (bits(temp,12,0) == 0) {
+ tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
+ cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
+ } else {
+ tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
+ cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
+ }
+ data = mbits(tsbtemp,63,13);
+ if (bits(tsbtemp,12,12))
+ data |= ULL(1) << (13+bits(tsbtemp,3,0));
+ data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
+ mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
+ pkt->set(data);
+ break;
default:
doMmuReadError:
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 128402fdd..b8a891c6d 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -44,8 +44,10 @@ MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
case MISCREG_SOFTINT:
// Check if we are going to interrupt because of something
setReg(miscReg, val);
- tc->getCpuPtr()->post_interrupt(soft_interrupt);
- warn("Writing to softint not really supported, writing: %#x\n", val);
+ tc->getCpuPtr()->checkInterrupts = true;
+ tc->getCpuPtr()->post_interrupt(hstick_match);
+ if (val != 0x10000 && val != 0)
+ warn("Writing to softint not really supported, writing: %#x\n", val);
break;
case MISCREG_SOFTINT_CLR:
diff --git a/src/dev/sparc/SConscript b/src/dev/sparc/SConscript
index c37294f0c..63f29846a 100644
--- a/src/dev/sparc/SConscript
+++ b/src/dev/sparc/SConscript
@@ -38,6 +38,7 @@ sources = []
sources += Split('''
t1000.cc
+ mm_disk.cc
''')
# Convert file names to SCons File objects. This takes care of the
diff --git a/src/dev/sparc/mm_disk.cc b/src/dev/sparc/mm_disk.cc
new file mode 100644
index 000000000..9057c28be
--- /dev/null
+++ b/src/dev/sparc/mm_disk.cc
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * This device acts as a disk similar to the memory mapped disk device
+ * in legion. Any access is translated to an offset in the disk image.
+ */
+
+#include "base/trace.hh"
+#include "dev/sparc/mm_disk.hh"
+#include "dev/platform.hh"
+#include "mem/port.hh"
+#include "mem/packet_access.hh"
+#include "sim/builder.hh"
+#include "sim/byteswap.hh"
+#include "sim/system.hh"
+
+MmDisk::MmDisk(Params *p)
+ : BasicPioDevice(p), image(p->image), curSector((uint64_t)-1), dirty(false)
+{
+ memset(&bytes, 0, SectorSize);
+ pioSize = image->size() * SectorSize;
+}
+
+Tick
+MmDisk::read(PacketPtr pkt)
+{
+ Addr accessAddr;
+ off_t sector;
+ off_t bytes_read;
+ uint16_t *d16;
+ uint32_t *d32;
+ uint64_t *d64;
+
+ assert(pkt->result == Packet::Unknown);
+ assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
+ accessAddr = pkt->getAddr() - pioAddr;
+
+ sector = accessAddr / SectorSize;
+
+ if (sector != curSector) {
+ if (dirty)
+ bytes_read = image->write(bytes, curSector);
+ bytes_read = image->read(bytes, sector);
+ curSector = sector;
+ }
+ switch (pkt->getSize()) {
+ case sizeof(uint8_t):
+ pkt->set(bytes[accessAddr % SectorSize]);
+ break;
+ case sizeof(uint16_t):
+ d16 = (uint16_t*)bytes + (accessAddr % SectorSize)/2;
+ pkt->set(htobe(*d16));
+ break;
+ case sizeof(uint32_t):
+ d32 = (uint32_t*)bytes + (accessAddr % SectorSize)/4;
+ pkt->set(htobe(*d32));
+ break;
+ case sizeof(uint64_t):
+ d64 = (uint64_t*)bytes + (accessAddr % SectorSize)/8;
+ pkt->set(htobe(*d64));
+ break;
+ default:
+ panic("Invalid access size\n");
+ }
+
+ pkt->result = Packet::Success;
+ return pioDelay;
+}
+
+Tick
+MmDisk::write(PacketPtr pkt)
+{
+ panic("need to implement\n");
+}
+
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
+ Param<Addr> pio_addr;
+ Param<Tick> pio_latency;
+ Param<Addr> pio_size;
+ SimObjectParam<Platform *> platform;
+ SimObjectParam<System *> system;
+ SimObjectParam<DiskImage *> image;
+END_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(MmDisk)
+
+ INIT_PARAM(pio_addr, "Device Address"),
+ INIT_PARAM(pio_latency, "Programmed IO latency"),
+ INIT_PARAM(pio_size, "Size of address range"),
+ INIT_PARAM(platform, "platform"),
+ INIT_PARAM(system, "system object"),
+ INIT_PARAM(image, "disk image")
+
+END_INIT_SIM_OBJECT_PARAMS(MmDisk)
+
+CREATE_SIM_OBJECT(MmDisk)
+{
+ MmDisk::Params *p = new MmDisk::Params;
+ p->name = getInstanceName();
+ p->pio_addr = pio_addr;
+ p->pio_delay = pio_latency;
+ p->platform = platform;
+ p->system = system;
+ p->image = image;
+ return new MmDisk(p);
+}
+
+REGISTER_SIM_OBJECT("MmDisk", MmDisk)
diff --git a/src/dev/sparc/mm_disk.hh b/src/dev/sparc/mm_disk.hh
new file mode 100644
index 000000000..0a4626067
--- /dev/null
+++ b/src/dev/sparc/mm_disk.hh
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * This device acts as a disk similar to the memory mapped disk device
+ * in legion. Any access is translated to an offset in the disk image.
+ */
+
+#ifndef __DEV_SPARC_MM_DISK_HH__
+#define __DEV_SPARC_MM_DISK_HH__
+
+#include "base/range.hh"
+#include "dev/io_device.hh"
+#include "dev/disk_image.hh"
+
+class MmDisk : public BasicPioDevice
+{
+ private:
+ DiskImage *image;
+ off_t curSector;
+ bool dirty;
+ union {
+ uint8_t bytes[SectorSize];
+ uint32_t words[SectorSize/4];
+ };
+
+ public:
+ struct Params : public BasicPioDevice::Params
+ {
+ DiskImage *image;
+ };
+ protected:
+ const Params *params() const { return (const Params*)_params; }
+
+ public:
+ MmDisk(Params *p);
+
+ virtual Tick read(PacketPtr pkt);
+ virtual Tick write(PacketPtr pkt);
+};
+
+#endif //__DEV_SPARC_MM_DISK_HH__
+
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
index 79195d976..030f4abd8 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/python/m5/objects/T1000.py
@@ -5,6 +5,12 @@ from Uart import Uart8250
from Platform import Platform
from SimConsole import SimConsole, ConsoleListener
+
+class MmDisk(BasicPioDevice):
+ type = 'MmDisk'
+ image = Param.DiskImage("Disk Image")
+ pio_addr = 0x1F40000000
+
class T1000(Platform):
type = 'T1000'
system = Param.System(Parent.any, "system")
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-02 02:54:57 +0000