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-rw-r--r--src/arch/arm/isa.cc14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index d7d51b887..17c87ba84 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1338,9 +1338,17 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
tlbiOp.broadcast(tc);
return;
}
- // @todo: uncomment this to enable Virtualization
- // case MISCREG_TLBI_ALLE2IS:
- // case MISCREG_TLBI_ALLE2:
+ // AArch64 TLB Invalidate All, EL2, Inner Shareable
+ case MISCREG_TLBI_ALLE2:
+ case MISCREG_TLBI_ALLE2IS:
+ {
+ assert64(tc);
+ scr = readMiscReg(MISCREG_SCR, tc);
+
+ TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
+ tlbiOp(tc);
+ return;
+ }
// AArch64 TLB Invalidate All, EL1
case MISCREG_TLBI_ALLE1:
case MISCREG_TLBI_VMALLE1: