10 files changed, 10 insertions, 25 deletions

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index f0e40f690..9cc00a89e 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -282,11 +282,6 @@ TLB::regStats()
         .desc("DTB misses")
         ;
 
-    invalids
-        .name(name() + ".invalids")
-        .desc("DTB access violations")
-        ;
-
     accesses
         .name(name() + ".accesses")
         .desc("DTB accesses")
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index a779a492d..1bddd8497 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -108,7 +108,6 @@ class TLB : public BaseTLB
     mutable Stats::Scalar write_accesses;
     Stats::Formula hits;
     Stats::Formula misses;
-    Stats::Formula invalids;
     Stats::Formula accesses;
 
 
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index e01c06ae5..cf1230745 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -281,11 +281,6 @@ TLB::regStats()
         .desc("DTB misses")
         ;
 
-    invalids
-        .name(name() + ".invalids")
-        .desc("DTB access violations")
-        ;
-
     accesses
         .name(name() + ".accesses")
         .desc("DTB accesses")
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 68b1c0c75..e301cf666 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -105,7 +105,6 @@ class TLB : public BaseTLB
     mutable Stats::Scalar write_accesses;
     Stats::Formula hits;
     Stats::Formula misses;
-    Stats::Formula invalids;
     Stats::Formula accesses;
 
   public:
diff --git a/src/arch/power/tlb.cc b/src/arch/power/tlb.cc
index 292f13078..a0ff69391 100644
--- a/src/arch/power/tlb.cc
+++ b/src/arch/power/tlb.cc
@@ -265,11 +265,6 @@ TLB::regStats()
         .desc("DTB misses")
         ;
 
-    invalids
-        .name(name() + ".invalids")
-        .desc("DTB access violations")
-        ;
-
     accesses
         .name(name() + ".accesses")
         .desc("DTB accesses")
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 1794de626..4445995fc 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -123,7 +123,6 @@ class TLB : public BaseTLB
     mutable Stats::Scalar write_accesses;
     Stats::Formula hits;
     Stats::Formula misses;
-    Stats::Formula invalids;
     Stats::Formula accesses;
 
   public:
diff --git a/src/base/statistics.cc b/src/base/statistics.cc
index 59013ed34..ab351567c 100644
--- a/src/base/statistics.cc
+++ b/src/base/statistics.cc
@@ -238,12 +238,12 @@ Vector2dInfo::enable()
 
 Formula::Formula()
 {
-    setInit();
 }
 
 Formula::Formula(Temp r)
 {
     root = r;
+    setInit();
     assert(size());
 }
 
@@ -252,6 +252,7 @@ Formula::operator=(Temp r)
 {
     assert(!root && "Can't change formulas");
     root = r;
+    setInit();
     assert(size());
     return *this;
 }
@@ -261,8 +262,11 @@ Formula::operator+=(Temp r)
 {
     if (root)
         root = NodePtr(new BinaryNode<std::plus<Result> >(root, r));
-    else
+    else {
         root = r;
+        setInit();
+    }
+
     assert(size());
     return *this;
 }
diff --git a/src/dev/etherdevice.cc b/src/dev/etherdevice.cc
index 5341c02c4..59febcdc5 100644
--- a/src/dev/etherdevice.cc
+++ b/src/dev/etherdevice.cc
@@ -119,7 +119,7 @@ EtherDevice::regStats()
         .precision(0)
         ;
 
-   descDmaWrBytes
+    descDmaWrBytes
         .name(name() + ".descDmaWriteBytes")
         .desc("number of descriptor bytes write w/ DMA")
         .precision(0)
@@ -364,4 +364,5 @@ EtherDevice::regStats()
 
     txPacketRate = txPackets / simSeconds;
     rxPacketRate = rxPackets / simSeconds;
+    totPacketRate = totPackets / simSeconds;
 }
diff --git a/src/dev/ide_disk.hh b/src/dev/ide_disk.hh
index 1b455e8ad..78a9e1fe7 100644
--- a/src/dev/ide_disk.hh
+++ b/src/dev/ide_disk.hh
@@ -244,10 +244,6 @@ class IdeDisk : public SimObject
     Stats::Scalar dmaWriteFullPages;
     Stats::Scalar dmaWriteBytes;
     Stats::Scalar dmaWriteTxs;
-    Stats::Formula rdBandwidth;
-    Stats::Formula wrBandwidth;
-    Stats::Formula totBandwidth;
-    Stats::Formula totBytes;
 
   public:
     typedef IdeDiskParams Params;
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 62e8ae126..2f1088609 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -324,12 +324,14 @@ class BaseCache : public MemObject
     /** Total cycle latency of overall MSHR misses. */
     Stats::Formula overallMshrUncacheableLatency;
 
+#if 0
     /** The total number of MSHR accesses per command and thread. */
     Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
     /** The total number of demand MSHR accesses. */
     Stats::Formula demandMshrAccesses;
     /** The total number of MSHR accesses. */
     Stats::Formula overallMshrAccesses;
+#endif
 
     /** The miss rate in the MSHRs pre command and thread. */
     Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];