diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/x86/tlb.cc | 40 | ||||
| -rw-r--r-- | src/arch/x86/tlb.hh | 11 |
2 files changed, 47 insertions, 4 deletions
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc index 191e91a00..e954c9c73 100644 --- a/src/arch/x86/tlb.cc +++ b/src/arch/x86/tlb.cc @@ -332,7 +332,20 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, DPRINTF(TLB, "Paging enabled.\n"); // The vaddr already has the segment base applied. TlbEntry *entry = lookup(vaddr); + if (mode == Read) { + rdAccesses++; + } else { + wrAccesses++; + } if (!entry) { + DPRINTF(TLB, "Handling a TLB miss for " + "address %#x at pc %#x.\n", + vaddr, tc->instAddr()); + if (mode == Read) { + rdMisses++; + } else { + wrMisses++; + } if (FullSystem) { Fault fault = walker->start(tc, translation, req, mode); if (timing || fault != NoFault) { @@ -343,10 +356,6 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, entry = lookup(vaddr); assert(entry); } else { - DPRINTF(TLB, "Handling a TLB miss for " - "address %#x at pc %#x.\n", - vaddr, tc->instAddr()); - Process *p = tc->getProcessPtr(); TlbEntry newEntry; bool success = p->pTable->lookup(vaddr, newEntry); @@ -445,6 +454,29 @@ TLB::getWalker() } void +TLB::regStats() +{ + using namespace Stats; + + rdAccesses + .name(name() + ".rdAccesses") + .desc("TLB accesses on read requests"); + + wrAccesses + .name(name() + ".wrAccesses") + .desc("TLB accesses on write requests"); + + rdMisses + .name(name() + ".rdMisses") + .desc("TLB misses on read requests"); + + wrMisses + .name(name() + ".wrMisses") + .desc("TLB misses on write requests"); + +} + +void TLB::serialize(CheckpointOut &cp) const { // Only store the entries in use. diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index a134ad427..09cd6edc7 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -100,6 +100,12 @@ namespace X86ISA TlbEntryTrie trie; uint64_t lruSeq; + // Statistics + Stats::Scalar rdAccesses; + Stats::Scalar wrAccesses; + Stats::Scalar rdMisses; + Stats::Scalar wrMisses; + Fault translateInt(RequestPtr req, ThreadContext *tc); Fault translate(RequestPtr req, ThreadContext *tc, @@ -142,6 +148,11 @@ namespace X86ISA TlbEntry * insert(Addr vpn, TlbEntry &entry); + /* + * Function to register Stats + */ + void regStats(); + // Checkpointing void serialize(CheckpointOut &cp) const override; void unserialize(CheckpointIn &cp) override; |