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-rw-r--r--src/arch/x86/utility.cc16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index f7358341b..8f1a419f1 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -261,9 +261,9 @@ uint64_t
getRFlags(ThreadContext *tc)
{
const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS));
- const uint64_t cc_flags(tc->readIntReg(X86ISA::CCREG_ZAPS));
- const uint64_t cfof_bits(tc->readIntReg(X86ISA::CCREG_CFOF));
- const uint64_t df_bit(tc->readIntReg(X86ISA::CCREG_DF));
+ const uint64_t cc_flags(tc->readCCReg(X86ISA::CCREG_ZAPS));
+ const uint64_t cfof_bits(tc->readCCReg(X86ISA::CCREG_CFOF));
+ const uint64_t df_bit(tc->readCCReg(X86ISA::CCREG_DF));
// ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to
// microcode, so we can safely ignore them.
@@ -276,13 +276,13 @@ getRFlags(ThreadContext *tc)
void
setRFlags(ThreadContext *tc, uint64_t val)
{
- tc->setIntReg(X86ISA::CCREG_ZAPS, val & ccFlagMask);
- tc->setIntReg(X86ISA::CCREG_CFOF, val & cfofMask);
- tc->setIntReg(X86ISA::CCREG_DF, val & DFBit);
+ tc->setCCReg(X86ISA::CCREG_ZAPS, val & ccFlagMask);
+ tc->setCCReg(X86ISA::CCREG_CFOF, val & cfofMask);
+ tc->setCCReg(X86ISA::CCREG_DF, val & DFBit);
// Internal microcode registers (ECF & EZF)
- tc->setIntReg(X86ISA::CCREG_ECF, 0);
- tc->setIntReg(X86ISA::CCREG_EZF, 0);
+ tc->setCCReg(X86ISA::CCREG_ECF, 0);
+ tc->setCCReg(X86ISA::CCREG_EZF, 0);
// Update the RFLAGS misc reg with whatever didn't go into the
// magic registers.