diff options
Diffstat (limited to 'src')
| -rwxr-xr-x | src/arch/isa_parser.py | 4 | ||||
| -rw-r--r-- | src/cpu/checker/cpu.cc | 4 |
2 files changed, 5 insertions, 3 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 87e02cb31..aa773ae80 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -856,7 +856,9 @@ class PCStateOperand(Operand): ctype = 'TheISA::PCState' if self.isPCPart(): ctype = self.ctype - return "%s %s;\n" % (ctype, self.base_name) + # Note that initializations in the declarations are solely + # to avoid 'uninitialized variable' errors from the compiler. + return '%s %s = 0;\n' % (ctype, self.base_name) def isPCState(self): return 1 diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index c6dacf9db..61c127ec4 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -298,10 +298,10 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size, // Cannot check this is actually what went to memory because // there stores can be in ld/st queue or coherent operations // overwriting values. - bool extraData; + bool extraData = false; if (unverifiedReq) { extraData = unverifiedReq->extraDataValid() ? - unverifiedReq->getExtraData() : 1; + unverifiedReq->getExtraData() : true; } if (unverifiedReq && unverifiedMemData && |