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-rw-r--r--src/cpu/o3/mem_dep_unit.hh2
-rw-r--r--src/cpu/o3/mem_dep_unit_impl.hh13
-rw-r--r--src/cpu/ozone/cpu.hh4
-rw-r--r--src/cpu/ozone/thread_state.hh2
-rw-r--r--src/dev/isa_fake.cc9
-rw-r--r--src/dev/isa_fake.hh2
-rw-r--r--src/mem/bus.cc10
-rw-r--r--src/mem/bus.hh4
-rw-r--r--src/mem/cache/base_cache.cc22
-rw-r--r--src/mem/cache/base_cache.hh33
-rw-r--r--src/python/m5/__init__.py4
-rw-r--r--src/python/m5/objects/Tsunami.py1
12 files changed, 81 insertions, 25 deletions
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index e399f0133..a12a3001b 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -69,7 +69,7 @@ class MemDepUnit {
typedef typename Impl::DynInstPtr DynInstPtr;
/** Empty constructor. Must call init() prior to using in this case. */
- MemDepUnit() {}
+ MemDepUnit();
/** Constructs a MemDepUnit with given parameters. */
MemDepUnit(Params *params);
diff --git a/src/cpu/o3/mem_dep_unit_impl.hh b/src/cpu/o3/mem_dep_unit_impl.hh
index c649ca385..f19980fd5 100644
--- a/src/cpu/o3/mem_dep_unit_impl.hh
+++ b/src/cpu/o3/mem_dep_unit_impl.hh
@@ -34,6 +34,13 @@
#include "cpu/o3/mem_dep_unit.hh"
template <class MemDepPred, class Impl>
+MemDepUnit<MemDepPred, Impl>::MemDepUnit()
+ : loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
+ storeBarrierSN(0), iqPtr(NULL)
+{
+}
+
+template <class MemDepPred, class Impl>
MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
: depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
@@ -160,8 +167,12 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
// producing memrefs/stores.
InstSeqNum producing_store;
if (inst->isLoad() && loadBarrier) {
+ DPRINTF(MemDepUnit, "Load barrier [sn:%lli] in flight\n",
+ loadBarrierSN);
producing_store = loadBarrierSN;
} else if (inst->isStore() && storeBarrier) {
+ DPRINTF(MemDepUnit, "Store barrier [sn:%lli] in flight\n",
+ storeBarrierSN);
producing_store = storeBarrierSN;
} else {
producing_store = depPred.checkInst(inst->readPC());
@@ -171,10 +182,12 @@ MemDepUnit<MemDepPred, Impl>::insert(DynInstPtr &inst)
// If there is a producing store, try to find the entry.
if (producing_store != 0) {
+ DPRINTF(MemDepUnit, "Searching for producer\n");
MemDepHashIt hash_it = memDepHash.find(producing_store);
if (hash_it != memDepHash.end()) {
store_entry = (*hash_it).second;
+ DPRINTF(MemDepUnit, "Proucer found\n");
}
}
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 828c2b4ca..ccb467394 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -363,8 +363,8 @@ class OzoneCPU : public BaseCPU
bool interval_stats;
- AlphaITB *itb;
- AlphaDTB *dtb;
+ TheISA::ITB *itb;
+ TheISA::DTB *dtb;
System *system;
PhysicalMemory *physmem;
#endif
diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh
index c4d16b3af..a71795851 100644
--- a/src/cpu/ozone/thread_state.hh
+++ b/src/cpu/ozone/thread_state.hh
@@ -122,7 +122,7 @@ struct OzoneThreadState : public ThreadState {
MiscReg readMiscRegWithEffect(int misc_reg)
{
- return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
+ return miscRegFile.readRegWithEffect(misc_reg, tc);
}
void setMiscReg(int misc_reg, const MiscReg &val)
diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc
index 103fdd8ce..40909c6a1 100644
--- a/src/dev/isa_fake.cc
+++ b/src/dev/isa_fake.cc
@@ -50,15 +50,6 @@ IsaFake::IsaFake(Params *p)
memset(&retData, p->retData, sizeof(retData));
}
-void
-IsaFake::init()
-{
- // Only init this device if it's connected to anything.
- if (pioPort)
- PioDevice::init();
-}
-
-
Tick
IsaFake::read(PacketPtr pkt)
{
diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh
index c4072e42c..e35b9c58f 100644
--- a/src/dev/isa_fake.hh
+++ b/src/dev/isa_fake.hh
@@ -80,8 +80,6 @@ class IsaFake : public BasicPioDevice
* @param data the data to not write.
*/
virtual Tick write(PacketPtr pkt);
-
- void init();
};
#endif // __ISA_FAKE_HH__
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 28ee3476b..7b65d252b 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -240,10 +240,10 @@ Bus::recvRetry(int id)
busIdle.reschedule(tickNextIdle);
}
}
- //If we weren't able to drain before, we might be able to now.
- if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle)
- drainEvent->process();
}
+ //If we weren't able to drain before, we might be able to now.
+ if (drainEvent && retryList.size() == 0 && curTick >= tickNextIdle)
+ drainEvent->process();
}
Port *
@@ -521,10 +521,10 @@ Bus::drain(Event * de)
//waiting. We might be idle but have someone waiting if the device we
//contacted for a retry didn't actually retry.
if (curTick >= tickNextIdle && retryList.size() == 0) {
+ return 0;
+ } else {
drainEvent = de;
return 1;
- } else {
- return 0;
}
}
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 1d1cfde89..ff1d2545d 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -257,8 +257,8 @@ class Bus : public MemObject
Bus(const std::string &n, int bus_id, int _clock, int _width,
bool responder_set)
: MemObject(n), busId(bus_id), clock(_clock), width(_width),
- tickNextIdle(0), busIdle(this), inRetry(false), defaultPort(NULL),
- responderSet(responder_set)
+ tickNextIdle(0), drainEvent(NULL), busIdle(this), inRetry(false),
+ defaultPort(NULL), responderSet(responder_set)
{
//Both the width and clock period must be positive
if (width <= 0)
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 1c519fb86..c26d7782b 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -140,6 +140,9 @@ BaseCache::CachePort::recvRetry()
}
waitingOnRetry = false;
}
+ // Check if we're done draining once this list is empty
+ if (drainList.empty())
+ cache->checkDrain();
}
else if (!isCpuSide)
{
@@ -338,6 +341,10 @@ BaseCache::CacheEvent::process()
cachePort->drainList.push_back(pkt);
cachePort->waitingOnRetry = true;
}
+
+ // Check if we're done draining once this list is empty
+ if (cachePort->drainList.empty())
+ cachePort->cache->checkDrain();
}
const char *
@@ -599,3 +606,18 @@ BaseCache::regStats()
;
}
+
+unsigned int
+BaseCache::drain(Event *de)
+{
+ // Set status
+ if (!canDrain()) {
+ drainEvent = de;
+
+ changeState(SimObject::Draining);
+ return 1;
+ }
+
+ changeState(SimObject::Drained);
+ return 0;
+}
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 565280aef..ea7544fbb 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -105,6 +105,8 @@ class BaseCache : public MemObject
void clearBlocked();
+ bool canDrain() { return drainList.empty(); }
+
bool blocked;
bool mustSendRetry;
@@ -227,6 +229,9 @@ class BaseCache : public MemObject
/** The number of misses to trigger an exit event. */
Counter missCount;
+ /** The drain event. */
+ Event *drainEvent;
+
public:
// Statistics
/**
@@ -340,7 +345,7 @@ class BaseCache : public MemObject
BaseCache(const std::string &name, Params &params)
: MemObject(name), blocked(0), blockedSnoop(0), masterRequests(0),
slaveRequests(0), blkSize(params.blkSize),
- missCount(params.maxMisses)
+ missCount(params.maxMisses), drainEvent(NULL)
{
//Start ports at null if more than one is created we should panic
cpuSidePort = NULL;
@@ -477,6 +482,7 @@ class BaseCache : public MemObject
{
uint8_t flag = 1<<cause;
masterRequests &= ~flag;
+ checkDrain();
}
/**
@@ -512,6 +518,7 @@ class BaseCache : public MemObject
{
uint8_t flag = 1<<cause;
slaveRequests &= ~flag;
+ checkDrain();
}
/**
@@ -589,6 +596,30 @@ class BaseCache : public MemObject
return;
}
}
+
+ virtual unsigned int drain(Event *de);
+
+ void checkDrain()
+ {
+ if (drainEvent && canDrain()) {
+ drainEvent->process();
+ changeState(SimObject::Drained);
+ // Clear the drain event
+ drainEvent = NULL;
+ }
+ }
+
+ bool canDrain()
+ {
+ if (doMasterRequest() || doSlaveRequest()) {
+ return false;
+ } else if (memSidePort && !memSidePort->canDrain()) {
+ return false;
+ } else if (cpuSidePort && !cpuSidePort->canDrain()) {
+ return false;
+ }
+ return true;
+ }
};
#endif //__BASE_CACHE_HH__
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index d41fd5a61..42abfe2cc 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -171,10 +171,10 @@ def switchCpus(cpuList):
for cpu in old_cpus:
if not isinstance(cpu, objects.BaseCPU):
- raise TypeError, "%s is not of type BaseCPU", cpu
+ raise TypeError, "%s is not of type BaseCPU" % cpu
for cpu in new_cpus:
if not isinstance(cpu, objects.BaseCPU):
- raise TypeError, "%s is not of type BaseCPU", cpu
+ raise TypeError, "%s is not of type BaseCPU" % cpu
# Drain all of the individual CPUs
drain_event = cc_main.createCountedDrain()
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
index 78ab65b31..ffe93727b 100644
--- a/src/python/m5/objects/Tsunami.py
+++ b/src/python/m5/objects/Tsunami.py
@@ -76,6 +76,7 @@ class Tsunami(Platform):
self.pchip.pio = bus.port
self.pciconfig.pio = bus.default
bus.responder_set = True
+ bus.responder = self.pciconfig
self.fake_sm_chip.pio = bus.port
self.fake_uart1.pio = bus.port
self.fake_uart2.pio = bus.port
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-15 13:45:16 +0000