diff options
Diffstat (limited to 'system/arm/aarch64_bootloader')
| -rw-r--r-- | system/arm/aarch64_bootloader/LICENSE.txt | 28 | ||||
| -rw-r--r-- | system/arm/aarch64_bootloader/boot.S | 124 | ||||
| -rw-r--r-- | system/arm/aarch64_bootloader/makefile | 4 |
3 files changed, 156 insertions, 0 deletions
diff --git a/system/arm/aarch64_bootloader/LICENSE.txt b/system/arm/aarch64_bootloader/LICENSE.txt new file mode 100644 index 000000000..d68a74e44 --- /dev/null +++ b/system/arm/aarch64_bootloader/LICENSE.txt @@ -0,0 +1,28 @@ +Copyright (c) 2012, ARM Limited +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of ARM nor the names of its contributors may be + used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/system/arm/aarch64_bootloader/boot.S b/system/arm/aarch64_bootloader/boot.S new file mode 100644 index 000000000..78d9710d4 --- /dev/null +++ b/system/arm/aarch64_bootloader/boot.S @@ -0,0 +1,124 @@ +/* + * boot.S - simple register setup code for stand-alone Linux booting + * + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE.txt file. + */ + + .text + + .globl _start +_start: + /* + * EL3 initialisation + */ + mrs x0, CurrentEL + cmp x0, #0xc // EL3? + b.ne start_ns // skip EL3 initialisation + + mov x0, #0x30 // RES1 + orr x0, x0, #(1 << 0) // Non-secure EL1 + orr x0, x0, #(1 << 8) // HVC enable + orr x0, x0, #(1 << 10) // 64-bit EL2 + msr scr_el3, x0 + + msr cptr_el3, xzr // Disable copro. traps to EL3 + + ldr x0, =CNTFRQ + msr cntfrq_el0, x0 + + /* + * Check for the primary CPU to avoid a race on the distributor + * registers. + */ + mrs x0, mpidr_el1 + tst x0, #15 + b.ne 1f // secondary CPU + + ldr x1, =GIC_DIST_BASE // GICD_CTLR + mov w0, #3 // EnableGrp0 | EnableGrp1 + str w0, [x1] + +1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR + mov w0, #~0 // Grp1 interrupts + str w0, [x1], #4 + b.ne 2f // Only local interrupts for secondary CPUs + str w0, [x1], #4 + str w0, [x1], #4 + +2: ldr x1, =GIC_CPU_BASE // GICC_CTLR + ldr w0, [x1] + mov w0, #3 // EnableGrp0 | EnableGrp1 + str w0, [x1] + + mov w0, #1 << 7 // allow NS access to GICC_PMR + str w0, [x1, #4] // GICC_PMR + + msr sctlr_el2, xzr + + /* + * Prepare the switch to the EL2_SP1 mode from EL3 + */ + ldr x0, =start_ns // Return after mode switch + mov x1, #0x3c9 // EL2_SP1 | D | A | I | F + msr elr_el3, x0 + msr spsr_el3, x1 + eret + +start_ns: + /* + * Kernel parameters + */ + mov x0, xzr + mov x1, xzr + mov x2, xzr + mov x3, xzr + + mrs x4, mpidr_el1 + tst x4, #15 + b.eq 2f + + /* + * Secondary CPUs + */ +1: wfe + ldr x4, =PHYS_OFFSET + 0xfff8 + ldr x4, [x4] + cbz x4, 1b + br x4 // branch to the given address + +2: + /* + * UART initialisation (38400 8N1) + */ + ldr x4, =UART_BASE // UART base + mov w5, #0x10 // ibrd + str w5, [x4, #0x24] + mov w5, #0xc300 + orr w5, w5, #0x0001 // cr + str w5, [x4, #0x30] + + /* + * CLCD output site MB + */ + ldr x4, =SYSREGS_BASE + ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB + str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA + str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL + + // set up the arch timer frequency + //ldr x0, =CNTFRQ + //msr cntfrq_el0, x0 + + /* + * Primary CPU + */ + ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob + ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address + br x6 + + .ltorg + + .org 0x200 diff --git a/system/arm/aarch64_bootloader/makefile b/system/arm/aarch64_bootloader/makefile new file mode 100644 index 000000000..4428d2620 --- /dev/null +++ b/system/arm/aarch64_bootloader/makefile @@ -0,0 +1,4 @@ +build: + aarch64-linux-gnu-gcc -c -DPHYS_OFFSET=0x80000000 -DCNTFRQ=0x01800000 -DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000 -DGIC_DIST_BASE=0x2c001000 -DGIC_CPU_BASE=0x2c002000 -Dkernel=0x80080000 -Dmbox=0x8000fff8 -Ddtb=0x80000100 -o boot_emm.o -march=armv8-a boot.S + aarch64-linux-gnu-ld -o boot_emm.arm64 -N -Ttext 0x00000010 boot_emm.o -non_shared -static + rm boot_emm.o
\ No newline at end of file |