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Diffstat (limited to 'system/arm/dt/armv7.dts')
| -rw-r--r-- | system/arm/dt/armv7.dts | 143 |
1 files changed, 143 insertions, 0 deletions
diff --git a/system/arm/dt/armv7.dts b/system/arm/dt/armv7.dts new file mode 100644 index 000000000..9bd5b39a1 --- /dev/null +++ b/system/arm/dt/armv7.dts @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2015 ARM Limited + * All rights reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Andreas Sandberg + */ + +/dts-v1/; + +#include CONF_PLATFORM + +#define CPU(n) \ + cpu@ ## n { \ + device_type = "cpu"; \ + compatible = "gem5,arm", "arm,cortex-a15"; \ + reg = < n >; \ + }; + +/ { + model = "V2P-CA15"; + compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0x4 0x00000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + #if CONF_CPUS > 0 + CPU(0) + #endif + #if CONF_CPUS > 1 + CPU(1) + #endif + #if CONF_CPUS > 2 + CPU(2) + #endif + #if CONF_CPUS > 3 + CPU(3) + #endif + #if CONF_CPUS > 4 + CPU(4) + #endif + #if CONF_CPUS > 5 + CPU(5) + #endif + #if CONF_CPUS > 6 + CPU(6) + #endif + #if CONF_CPUS > 7 + CPU(7) + #endif + #if CONF_CPUS > 8 + CPU(8) + #endif + #if CONF_CPUS > 9 + CPU(9) + #endif + #if CONF_CPUS > 10 + CPU(10) + #endif + #if CONF_CPUS > 11 + CPU(11) + #endif + #if CONF_CPUS > 12 + CPU(12) + #endif + #if CONF_CPUS > 13 + CPU(13) + #endif + #if CONF_CPUS > 14 + CPU(14) + #endif + #if CONF_CPUS > 15 + CPU(15) + #endif + #if CONF_CPUS > 16 + #error Unsupported number of CPUs + #endif + }; + + virt-encoder { + compatible = "gem5,hdlcd-virt-encoder"; + port { + hdlcd0_virt_input: endpoint@0 { + remote-endpoint = <&hdlcd0_output>; + }; + }; + + display-timings { + native-mode = <&timing0>; + + timing0: timing_1080p60 { + /* 1920x1080-60 */ + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <148>; + hback-porch = <88>; + hsync-len = <44>; + vfront-porch = <36>; + vback-porch = <4>; + vsync-len = <5>; + }; + }; + }; +}; + +&hdlcd0 { + status = "ok"; + + port { + hdlcd0_output: endpoint@0 { + remote-endpoint = <&hdlcd0_virt_input>; + }; + }; +}; |