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-rw-r--r--system/alpha/console/Makefile60
-rw-r--r--system/alpha/console/console.c1074
-rw-r--r--system/alpha/console/dbmentry.S213
-rw-r--r--system/alpha/console/paljtokern.S174
-rw-r--r--system/alpha/console/paljtoslave.S161
-rw-r--r--system/alpha/console/printf.c301
-rw-r--r--system/alpha/h/cserve.h52
-rw-r--r--system/alpha/h/dc21164FromGasSources.h886
-rw-r--r--system/alpha/h/ev5_alpha_defs.h314
-rw-r--r--system/alpha/h/ev5_defs.h598
-rw-r--r--system/alpha/h/ev5_impure.h420
-rw-r--r--system/alpha/h/ev5_osfalpha_defs.h152
-rw-r--r--system/alpha/h/ev5_paldef.h162
-rw-r--r--system/alpha/h/fromHudsonMacros.h88
-rw-r--r--system/alpha/h/fromHudsonOsf.h483
-rw-r--r--system/alpha/h/rpb.h387
-rw-r--r--system/alpha/h/tlaser.h34
-rw-r--r--system/alpha/palcode/Makefile92
-rw-r--r--system/alpha/palcode/osfpal.S4202
-rw-r--r--system/alpha/palcode/platform.S2337
20 files changed, 12190 insertions, 0 deletions
diff --git a/system/alpha/console/Makefile b/system/alpha/console/Makefile
new file mode 100644
index 000000000..9fea133a2
--- /dev/null
+++ b/system/alpha/console/Makefile
@@ -0,0 +1,60 @@
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan L. Binkert
+# Ali G. Saidi
+
+# Point to the M5 diretory so we can get some headers
+M5?=../../..
+
+### If we are not compiling on an alpha, we must use cross tools ###
+ifneq ($(shell uname -m), alpha)
+CROSS_COMPILE?=alpha-unknown-linux-gnu-
+endif
+CC=$(CROSS_COMPILE)gcc
+AS=$(CROSS_COMPILE)as
+LD=$(CROSS_COMPILE)ld
+
+DBMENTRY= fffffc0000010000
+CFLAGS=-I . -I ../h -I$(M5)/src/dev/alpha -I$(M5)/util/m5/ -fno-builtin -Wa,-m21164
+OBJS=dbmentry.o printf.o paljtokern.o paljtoslave.o console.o m5op.o
+
+all: console
+
+m5op.o: $(M5)/util/m5/m5op_alpha.S
+ $(CC) $(CFLAGS) -nostdinc -o $@ -c $<
+
+%.o: %.S
+ $(CC) $(CFLAGS) -nostdinc -o $@ -c $<
+
+%.o: %.c
+ $(CC) -g3 $(CFLAGS) -o $@ -c $<
+
+console: $(OBJS)
+ $(LD) -o console -N -Ttext $(DBMENTRY) -non_shared $(OBJS) -lc
+
+clean:
+ rm -f *.o console
diff --git a/system/alpha/console/console.c b/system/alpha/console/console.c
new file mode 100644
index 000000000..f57ce054f
--- /dev/null
+++ b/system/alpha/console/console.c
@@ -0,0 +1,1074 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* ******************************************
+ * M5 Console
+ * ******************************************/
+
+#include <linux/stddef.h>
+#include <sys/types.h>
+
+#define CONSOLE
+#include "access.h"
+#include "cserve.h"
+#include "rpb.h"
+
+#define CONS_INT_TX 0x01 /* interrupt enable / state bits */
+#define CONS_INT_RX 0x02
+
+#define PAGE_SIZE (8192)
+
+#define KSTACK_REGION_VA 0x20040000
+
+#define KSEG 0xfffffc0000000000
+#define K1BASE 0xfffffc8000000000
+#define KSEG_TO_PHYS(x) (((ulong)x) & ~KSEG)
+
+#define ROUNDUP8(x) ((ulong)(((ulong)x)+7) & ~7)
+#define ROUNDUP128(x) ((ulong)(((ulong)x) + 127) & ~127)
+#define ROUNDUP8K(x) ((ulong)(((ulong)(x)) + 8191) & ~8191)
+
+#define FIRST(x) ((((ulong)(x)) >> 33) & 0x3ff)
+#define SECOND(x) ((((ulong)(x)) >> 23) & 0x3ff)
+#define THIRD(x) ((((ulong)(x)) >> 13) & 0x3ff)
+#define THIRD_XXX(x) ((((ulong)(x)) >> 13) & 0xfff)
+#define PFN(x) ((((ulong)(x) & ~KSEG) >> 13))
+
+/* Kernel write | kernel read | valid */
+#define KPTE(x) ((ulong)((((ulong)(x)) << 32) | 0x1101))
+
+#define HWRPB_PAGES 16
+
+#define NUM_KERNEL_THIRD (4)
+
+#define printf_lock(args...) \
+ do { \
+ SpinLock(&theLock); \
+ printf(args); \
+ SpinUnlock(&theLock); \
+ } while (0)
+
+
+void unixBoot(int argc, char **argv);
+void JToKern(char *bootadr, ulong rpb_percpu, ulong free_pfn, ulong k_argc,
+ char **k_argv, char **envp);
+void JToPal(ulong bootadr);
+void SlaveLoop(int cpu);
+
+volatile struct AlphaAccess *m5AlphaAccess;
+struct AlphaAccess m5Conf;
+
+ulong theLock;
+
+extern void SpinLock(ulong *lock);
+#define SpinUnlock(_x) *(_x) = 0;
+
+struct _kernel_params {
+ char *bootadr;
+ ulong rpb_percpu;
+ ulong free_pfn;
+ ulong argc;
+ ulong argv;
+ ulong envp; /* NULL */
+};
+
+extern consoleCallback[];
+extern consoleFixup[];
+long CallBackDispatcher();
+long CallBackFixup();
+
+/*
+ * m5 console output
+ */
+
+void
+InitConsole()
+{
+}
+
+char
+GetChar()
+{
+ return m5AlphaAccess->inputChar;
+}
+
+void
+PutChar(char c)
+{
+ m5AlphaAccess->outputChar = c;
+}
+
+int
+passArgs(int argc)
+{
+ return 0;
+}
+
+int
+main(int argc, char **argv)
+{
+ int x, i;
+ uint *k1ptr, *ksegptr;
+
+ InitConsole();
+ printf_lock("M5 console: m5AlphaAccess @ 0x%x\n", m5AlphaAccess);
+
+ /*
+ * get configuration from backdoor
+ */
+ m5Conf.last_offset = m5AlphaAccess->last_offset;
+ printf_lock("Got Configuration %d\n", m5Conf.last_offset);
+
+ m5Conf.last_offset = m5AlphaAccess->last_offset;
+ m5Conf.version = m5AlphaAccess->version;
+ m5Conf.numCPUs = m5AlphaAccess->numCPUs;
+ m5Conf.intrClockFrequency = m5AlphaAccess->intrClockFrequency;
+ m5Conf.cpuClock = m5AlphaAccess->cpuClock;
+ m5Conf.mem_size = m5AlphaAccess->mem_size;
+ m5Conf.kernStart = m5AlphaAccess->kernStart;
+ m5Conf.kernEnd = m5AlphaAccess->kernEnd;
+ m5Conf.entryPoint = m5AlphaAccess->entryPoint;
+ m5Conf.diskUnit = m5AlphaAccess->diskUnit;
+ m5Conf.diskCount = m5AlphaAccess->diskCount;
+ m5Conf.diskPAddr = m5AlphaAccess->diskPAddr;
+ m5Conf.diskBlock = m5AlphaAccess->diskBlock;
+ m5Conf.diskOperation = m5AlphaAccess->diskOperation;
+ m5Conf.outputChar = m5AlphaAccess->outputChar;
+ m5Conf.inputChar = m5AlphaAccess->inputChar;
+
+ if (m5Conf.version != ALPHA_ACCESS_VERSION) {
+ panic("Console version mismatch. Console expects %d. has %d \n",
+ ALPHA_ACCESS_VERSION, m5Conf.version);
+ }
+
+ /*
+ * setup arguments to kernel
+ */
+ unixBoot(argc, argv);
+
+ panic("unix failed to boot\n");
+ return 1;
+}
+
+/*
+ * BOOTING
+ */
+struct rpb m5_rpb = {
+ NULL, /* 000: physical self-reference */
+ ((long)'H') | (((long)'W') << 8) | (((long)'R') << 16) |
+ ((long)'P' << 24) | (((long)'B') << 32), /* 008: contains "HWRPB" */
+ 6, /* 010: HWRPB version number */
+ /* the byte count is wrong, but who needs it? - lance */
+ 0, /* 018: bytes in RPB perCPU CTB CRB MEDSC */
+ 0, /* 020: primary cpu id */
+ PAGE_SIZE, /* 028: page size in bytes */
+ 43, /* 030: number of phys addr bits */
+ 127, /* 038: max valid ASN */
+ {'0','0','0','0','0','0','0','0','0','0','0','0','0','0','0','1'},
+ /* 040: system serial num: 10 ascii chars */
+ 0, /* OVERRIDDEN */
+ (1<<10), /* 058: system variation */
+ 'c'|('o'<<8)|('o'<<16)|('l'<< 24), /* 060: system revision */
+ 1024*4096, /* 068: scaled interval clock intr freq */
+ 0, /* 070: cycle counter frequency */
+ 0x200000000, /* 078: virtual page table base */
+ 0, /* 080: reserved */
+ 0, /* 088: offset to translation buffer hint */
+ 1, /* 090: number of processor slots OVERRIDDEN*/
+ sizeof(struct rpb_percpu), /* 098: per-cpu slot size. OVERRIDDEN */
+ 0, /* 0A0: offset to per_cpu slots */
+ 1, /* 0A8: number of CTBs */
+ sizeof(struct ctb_tt),
+ 0, /* 0B8: offset to CTB (cons term block) */
+ 0, /* 0C0: offset to CRB (cons routine block) */
+ 0, /* 0C8: offset to memory descriptor table */
+ 0, /* 0D0: offset to config data block */
+ 0, /* 0D8: offset to FRU table */
+ 0, /* 0E0: virt addr of save term routine */
+ 0, /* 0E8: proc value for save term routine */
+ 0, /* 0F0: virt addr of restore term routine */
+ 0, /* 0F8: proc value for restore term routine */
+ 0, /* 100: virt addr of CPU restart routine */
+ 0, /* 108: proc value for CPU restart routine */
+ 0, /* 110: used to determine presence of kdebug */
+ 0, /* 118: reserved for hardware */
+/* the checksum is wrong, but who needs it? - lance */
+ 0, /* 120: checksum of prior entries in rpb */
+ 0, /* 128: receive ready bitmask */
+ 0, /* 130: transmit ready bitmask */
+ 0, /* 138: Dynamic System Recog. offset */
+};
+
+ulong m5_tbb[] = { 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e,
+ 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e,
+ 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e,
+ 0x1e1e1e1e1e1e1e1e, 0x1e1e1e1e1e1e1e1e };
+
+struct rpb_percpu m5_rpb_percpu = {
+ {0,0,0,0,0,0,1,{0,0},{0,0,0,0,0,0,0,0}}, /* 000: boot/restart HWPCB */
+ (STATE_PA | STATE_PP | STATE_CV |
+ STATE_PV | STATE_PMV | STATE_PL), /* 080: per-cpu state bits */
+ 0xc000, /* 088: palcode memory length */
+ 0x2000, /* 090: palcode scratch length */
+ 0x4000, /* 098: paddr of pal mem space */
+ 0x2000, /* 0A0: paddr of pal scratch space */
+ (2 << 16) | (5 << 8) | 1, /* 0A8: PALcode rev required */
+ 11 | (2L << 32), /* 0B0: processor type */
+ 7, /* 0B8: processor variation */
+ 'M'|('5'<<8)|('A'<<16)|('0'<<24), /* 0C0: processor revision */
+ {'M','5','/','A','l','p','h','a','0','0','0','0','0','0','0','0'},
+ /* 0C8: proc serial num: 10 chars */
+ 0, /* 0D8: phys addr of logout area */
+ 0, /* 0E0: len in bytes of logout area */
+ 0, /* 0E8: halt pcb base */
+ 0, /* 0F0: halt pc */
+ 0, /* 0F8: halt ps */
+ 0, /* 100: halt arg list (R25) */
+ 0, /* 108: halt return address (R26) */
+ 0, /* 110: halt procedure value (R27) */
+ 0, /* 118: reason for halt */
+ 0, /* 120: for software */
+ {0}, /* 128: inter-console comm buffer */
+ {1,0,5,0,0,0,0,0,0,0,0,0,0,0,0,0}, /* 1D0: PALcode revs available */
+ 0 /* 250: reserved for arch use */
+/* the dump stack grows from the end of the rpb page not to reach here */
+};
+
+struct _m5_rpb_mdt {
+ long rpb_checksum; /* 000: checksum of entire mem desc table */
+ long rpb_impaddr; /* 008: PA of implementation dep info */
+ long rpb_numcl; /* 010: number of clusters */
+ struct rpb_cluster rpb_cluster[3]; /* first instance of a cluster */
+};
+
+struct _m5_rpb_mdt m5_rpb_mdt = {
+ 0, /* 000: checksum of entire mem desc table */
+ 0, /* 008: PA of implementation dep info */
+ 0, /* 010: number of clusters */
+ {{ 0, /* 000: starting PFN of this cluster */
+ 0, /* 008: count of PFNs in this cluster */
+ 0, /* 010: count of tested PFNs in cluster */
+ 0, /* 018: va of bitmap */
+ 0, /* 020: pa of bitmap */
+ 0, /* 028: checksum of bitmap */
+ 1 /* 030: usage of cluster */
+ },
+ { 0, /* 000: starting PFN of this cluster */
+ 0, /* 008: count of PFNs in this cluster */
+ 0, /* 010: count of tested PFNs in cluster */
+ 0, /* 018: va of bitmap */
+ 0, /* 020: pa of bitmap */
+ 0, /* 028: checksum of bitmap */
+ 0 /* 030: usage of cluster */
+ },
+ { 0, /* 000: starting PFN of this cluster */
+ 0, /* 008: count of PFNs in this cluster */
+ 0, /* 010: count of tested PFNs in cluster */
+ 0, /* 018: va of bitmap */
+ 0, /* 020: pa of bitmap */
+ 0, /* 028: checksum of bitmap */
+ 0 /* 030: usage of cluster */
+ }}
+};
+
+/* constants for slotinfo bus_type subfield */
+#define SLOTINFO_TC 0
+#define SLOTINFO_ISA 1
+#define SLOTINFO_EISA 2
+#define SLOTINFO_PCI 3
+
+struct rpb_ctb m5_rpb_ctb = {
+ CONS_DZ, /* 000: console type */
+ 0, /* 008: console unit */
+ 0, /* 010: reserved */
+ 0 /* 018: byte length of device dep portion */
+};
+
+/* we don't do any fixup (aka relocate the console) - we hope */
+struct rpb_crb m5_rpb_crb = {
+ 0, /* va of call-back dispatch rtn */
+ 0, /* pa of call-back dispatch rtn */
+ 0, /* va of call-back fixup rtn */
+ 0, /* pa of call-back fixup rtn */
+ 0, /* number of entries in phys/virt map */
+ 0 /* Number of pages to be mapped */
+};
+
+struct _rpb_name {
+ ulong length;
+ char name[16];
+};
+
+extern struct _rpb_name m5_name;
+
+struct rpb_dsr m5_rpb_dsr = {
+ 0,
+ 0,
+ 0,
+};
+
+struct _rpb_name m5_name = {
+ 16,
+ {'U','M','I','C','H',' ','M','5','/','A','L','P','H','A',' ',0},
+};
+
+/*
+ * M5 has one LURT entry:
+ * 1050 is for workstations
+ * 1100 is servers (and is needed for CXX)
+ */
+long m5_lurt[10] = { 9, 12, -1, -1, -1, -1, -1, -1, 1100, 1100 };
+
+ulong unix_boot_mem;
+ulong bootadr;
+
+char **kargv;
+int kargc;
+ulong free_pfn;
+struct rpb_percpu *rpb_percpu;
+
+char *
+unix_boot_alloc(int pages)
+{
+ char *ret = (char *)unix_boot_mem;
+ unix_boot_mem += (pages * PAGE_SIZE);
+ return ret;
+}
+
+ulong *first = 0;
+ulong *third_rpb = 0;
+ulong *reservedFixup = 0;
+
+int strcpy(char *dst, char *src);
+
+struct rpb *rpb;
+extern ulong _end;
+
+void
+unixBoot(int argc, char **argv)
+{
+ ulong *second, *third_kernel, ptr, *tbb, size, *percpu_logout;
+ unsigned char *mdt_bitmap;
+ long *lp1, *lp2, sum;
+ int i, cl;
+ ulong kern_first_page;
+ ulong mem_size = m5Conf.mem_size;
+
+ ulong mem_pages = mem_size / PAGE_SIZE, cons_pages;
+ ulong mdt_bitmap_pages = mem_pages / (PAGE_SIZE*8);
+
+ ulong kernel_bytes, ksp, kernel_end, *unix_kernel_stack, bss,
+ ksp_bottom, ksp_top;
+ struct rpb_ctb *rpb_ctb;
+ struct ctb_tt *ctb_tt;
+ struct rpb_dsr *rpb_dsr;
+ struct rpb_crb *rpb_crb;
+ struct _m5_rpb_mdt *rpb_mdt;
+ int *rpb_lurt;
+ char *rpb_name;
+ ulong nextPtr;
+
+ printf_lock("memsize %x pages %x \n", mem_size, mem_pages);
+
+ /* Allocate:
+ * two pages for the HWRPB
+ * five page table pages:
+ * 1: First level page table
+ * 1: Second level page table
+ * 1: Third level page table for HWRPB
+ * 2: Third level page table for kernel (for up to 16MB)
+ * set up the page tables
+ * load the kernel at the physical address 0x230000
+ * build the HWRPB
+ * set up memory descriptor table to give up the
+ * physical memory between the end of the page
+ * tables and the start of the kernel
+ * enable kseg addressing
+ * jump to the kernel
+ */
+
+ unix_boot_mem = ROUNDUP8K(&_end);
+
+ printf_lock("First free page after ROM 0x%x\n", unix_boot_mem);
+
+ rpb = (struct rpb *)unix_boot_alloc(HWRPB_PAGES);
+
+ mdt_bitmap = (unsigned char *)unix_boot_alloc(mdt_bitmap_pages);
+ first = (ulong *)unix_boot_alloc(1);
+ second = (ulong *)unix_boot_alloc(1);
+ third_rpb = (ulong *)unix_boot_alloc(1);
+ reservedFixup = (ulong*) unix_boot_alloc(1);
+ third_kernel = (ulong *)unix_boot_alloc(NUM_KERNEL_THIRD);
+ percpu_logout = (ulong*)unix_boot_alloc(1);
+
+ cons_pages = KSEG_TO_PHYS(unix_boot_mem) / PAGE_SIZE;
+
+ /* Set up the page tables */
+ bzero((char *)first, PAGE_SIZE);
+ bzero((char *)second, PAGE_SIZE);
+ bzero((char *)reservedFixup, PAGE_SIZE);
+ bzero((char *)third_rpb, HWRPB_PAGES * PAGE_SIZE);
+ bzero((char *)third_kernel, PAGE_SIZE * NUM_KERNEL_THIRD);
+
+ first[0] = KPTE(PFN(second));
+ first[1] = KPTE(PFN(first)); /* Region 3 */
+
+ /* Region 0 */
+ second[SECOND(0x10000000)] = KPTE(PFN(third_rpb));
+
+ for (i = 0; i < NUM_KERNEL_THIRD; i++) {
+ /* Region 1 */
+ second[SECOND(0x20000000) + i] = KPTE(PFN(third_kernel) + i);
+ }
+
+ /* Region 2 */
+ second[SECOND(0x40000000)] = KPTE(PFN(second));
+
+
+ /* For some obscure reason, Dec Unix's database read
+ * from /etc/sysconfigtab is written to this fixed
+ * mapped memory location. Go figure, since it is
+ * not initialized by the console. Maybe it is
+ * to look at the database from the console
+ * after a boot/crash.
+ *
+ * Black magic to estimate the max size. SEGVs on overflow
+ * bugnion
+ */
+
+#define DATABASE_BASE 0x20000000
+#define DATABASE_END 0x20020000
+
+ ulong *dbPage = (ulong*)unix_boot_alloc(1);
+ bzero(dbPage, PAGE_SIZE);
+ second[SECOND(DATABASE_BASE)] = KPTE(PFN(dbPage));
+ for (i = DATABASE_BASE; i < DATABASE_END ; i += PAGE_SIZE) {
+ ulong *db = (ulong*)unix_boot_alloc(1);
+ dbPage[THIRD(i)] = KPTE(PFN(db));
+ }
+
+ /* Region 0 */
+ /* Map the HWRPB */
+ for (i = 0; i < HWRPB_PAGES; i++)
+ third_rpb[i] = KPTE(PFN(rpb) + i);
+
+ /* Map the MDT bitmap table */
+ for (i = 0; i < mdt_bitmap_pages; i++) {
+ third_rpb[HWRPB_PAGES + i] = KPTE(PFN(mdt_bitmap) + i);
+ }
+
+ /* Protect the PAL pages */
+ for (i = 1; i < PFN(first); i++)
+ third_rpb[HWRPB_PAGES + mdt_bitmap_pages + i] = KPTE(i);
+
+ /* Set up third_kernel after it's loaded, when we know where it is */
+ kern_first_page = (KSEG_TO_PHYS(m5Conf.kernStart)/PAGE_SIZE);
+ kernel_end = ROUNDUP8K(m5Conf.kernEnd);
+ bootadr = m5Conf.entryPoint;
+
+ printf_lock("HWRPB 0x%x l1pt 0x%x l2pt 0x%x l3pt_rpb 0x%x l3pt_kernel 0x%x"
+ " l2reserv 0x%x\n",
+ rpb, first, second, third_rpb, third_kernel, reservedFixup);
+ if (kernel_end - m5Conf.kernStart > (0x800000*NUM_KERNEL_THIRD)) {
+ printf_lock("Kernel is more than 8MB 0x%x - 0x%x = 0x%x\n",
+ kernel_end, m5Conf.kernStart,
+ kernel_end - m5Conf.kernStart );
+ panic("kernel too big\n");
+ }
+ printf_lock("kstart = 0x%x, kend = 0x%x, kentry = 0x%x, numCPUs = 0x%x\n", m5Conf.kernStart, m5Conf.kernEnd, m5Conf.entryPoint, m5Conf.numCPUs);
+ ksp_bottom = (ulong)unix_boot_alloc(1);
+ ksp_top = ksp_bottom + PAGE_SIZE;
+ ptr = (ulong) ksp_bottom;
+ bzero((char *)ptr, PAGE_SIZE);
+ dbPage[THIRD(KSTACK_REGION_VA)] = 0; /* Stack Guard Page */
+ dbPage[THIRD(KSTACK_REGION_VA + PAGE_SIZE)] = KPTE(PFN(ptr)); /* Kernel Stack Page */
+ dbPage[THIRD(KSTACK_REGION_VA + 2*PAGE_SIZE)] = 0; /* Stack Guard Page */
+
+ /* put argv into the bottom of the stack - argv starts at 1 because
+ * the command thatr got us here (i.e. "unixboot) is in argv[0].
+ */
+ ksp = ksp_top - 8; /* Back up one longword */
+ ksp -= argc * sizeof(char *); /* Make room for argv */
+ kargv = (char **) ksp;
+ for (i = 1; i < argc; i++) { /* Copy arguments to stack */
+ ksp -= ((strlen(argv[i]) + 1) + 7) & ~0x7;
+ kargv[i-1] = (char *) ksp;
+ strcpy(kargv[i - 1], argv[i]);
+ }
+ kargc = i - 1;
+ kargv[kargc] = NULL; /* just to be sure; doesn't seem to be used */
+ ksp -= sizeof(char *); /* point above last arg for no real reason */
+
+ free_pfn = PFN(kernel_end);
+
+ bcopy((char *)&m5_rpb, (char *)rpb, sizeof(struct rpb));
+
+ rpb->rpb_selfref = (struct rpb *) KSEG_TO_PHYS(rpb);
+ rpb->rpb_string = 0x0000004250525748;
+
+ tbb = (ulong *) (((char *) rpb) + ROUNDUP8(sizeof(struct rpb)));
+ rpb->rpb_trans_off = (ulong)tbb - (ulong)rpb;
+ bcopy((char *)m5_tbb, (char *)tbb, sizeof(m5_tbb));
+
+ /*
+ * rpb_counter. Use to determine timeouts in OS.
+ * XXX must be patched after a checkpoint restore (I guess)
+ */
+
+ printf_lock("CPU Clock at %d MHz IntrClockFrequency=%d \n",
+ m5Conf.cpuClock, m5Conf.intrClockFrequency);
+ rpb->rpb_counter = m5Conf.cpuClock * 1000 * 1000;
+
+ /*
+ * By definition, the rpb_clock is scaled by 4096 (in hz)
+ */
+ rpb->rpb_clock = m5Conf.intrClockFrequency * 4096;
+
+ /*
+ * Per CPU Slots. Multiprocessor support.
+ */
+ int percpu_size = ROUNDUP128(sizeof(struct rpb_percpu));
+
+ printf_lock("Booting with %d processor(s) \n", m5Conf.numCPUs);
+
+ rpb->rpb_numprocs = m5Conf.numCPUs;
+ rpb->rpb_slotsize = percpu_size;
+ rpb_percpu = (struct rpb_percpu *)
+ ROUNDUP128(((ulong)tbb) + (sizeof(m5_tbb)));
+
+ rpb->rpb_percpu_off = (ulong)rpb_percpu - (ulong)rpb;
+
+ for (i = 0; i < m5Conf.numCPUs; i++) {
+ struct rpb_percpu *thisCPU = (struct rpb_percpu*)
+ ((ulong)rpb_percpu + percpu_size * i);
+
+ bzero((char *)thisCPU, percpu_size);
+ bcopy((char *)&m5_rpb_percpu, (char *)thisCPU,
+ sizeof(struct rpb_percpu));
+
+ thisCPU->rpb_pcb.rpb_ksp = (KSTACK_REGION_VA + 2*PAGE_SIZE - (ksp_top - ksp));
+ thisCPU->rpb_pcb.rpb_ptbr = PFN(first);
+
+ thisCPU->rpb_logout = KSEG_TO_PHYS(percpu_logout);
+ thisCPU->rpb_logout_len = PAGE_SIZE;
+
+ printf_lock("KSP: 0x%x PTBR 0x%x\n",
+ thisCPU->rpb_pcb.rpb_ksp, thisCPU->rpb_pcb.rpb_ptbr);
+ }
+
+ nextPtr = (ulong)rpb_percpu + percpu_size * m5Conf.numCPUs;
+
+ /*
+ * Console Terminal Block
+ */
+ rpb_ctb = (struct rpb_ctb *) nextPtr;
+ ctb_tt = (struct ctb_tt*) rpb_ctb;
+
+ rpb->rpb_ctb_off = ((ulong)rpb_ctb) - (ulong)rpb;
+ rpb->rpb_ctb_size = sizeof(struct rpb_ctb);
+
+ bzero((char *)rpb_ctb, sizeof(struct ctb_tt));
+
+ rpb_ctb->rpb_type = CONS_DZ;
+ rpb_ctb->rpb_length = sizeof(ctb_tt) - sizeof(rpb_ctb);
+
+ /*
+ * uart initizliation
+ */
+ ctb_tt->ctb_tintr_vec = 0x6c0; /* matches tlaser pal code */
+ ctb_tt->ctb_rintr_vec = 0x680; /* matches tlaser pal code */
+ ctb_tt->ctb_term_type = CTB_GRAPHICS;
+
+ rpb_crb = (struct rpb_crb *) (((ulong)rpb_ctb) + sizeof(struct ctb_tt));
+ rpb->rpb_crb_off = ((ulong)rpb_crb) - (ulong)rpb;
+
+ bzero((char *)rpb_crb, sizeof(struct rpb_crb));
+
+ /*
+ * console callback stuff (m5)
+ */
+ rpb_crb->rpb_num = 1;
+ rpb_crb->rpb_mapped_pages = HWRPB_PAGES;
+ rpb_crb->rpb_map[0].rpb_virt = 0x10000000;
+ rpb_crb->rpb_map[0].rpb_phys = KSEG_TO_PHYS(((ulong)rpb) & ~0x1fff);
+ rpb_crb->rpb_map[0].rpb_pgcount = HWRPB_PAGES;
+
+ printf_lock("Console Callback at 0x%x, fixup at 0x%x, crb offset: 0x%x\n",
+ rpb_crb->rpb_va_disp, rpb_crb->rpb_va_fixup, rpb->rpb_crb_off);
+
+ rpb_mdt = (struct _m5_rpb_mdt *)((ulong)rpb_crb + sizeof(struct rpb_crb));
+ rpb->rpb_mdt_off = (ulong)rpb_mdt - (ulong)rpb;
+ bcopy((char *)&m5_rpb_mdt, (char *)rpb_mdt, sizeof(struct _m5_rpb_mdt));
+
+
+ cl = 0;
+ rpb_mdt->rpb_cluster[cl].rpb_pfncount = kern_first_page;
+ cl++;
+
+ rpb_mdt->rpb_cluster[cl].rpb_pfn = kern_first_page;
+ rpb_mdt->rpb_cluster[cl].rpb_pfncount = mem_pages - kern_first_page;
+ rpb_mdt->rpb_cluster[cl].rpb_pfntested =
+ rpb_mdt->rpb_cluster[cl].rpb_pfncount;
+ rpb_mdt->rpb_cluster[cl].rpb_pa = KSEG_TO_PHYS(mdt_bitmap);
+ rpb_mdt->rpb_cluster[cl].rpb_va = 0x10000000 + HWRPB_PAGES * PAGE_SIZE;
+ cl++;
+
+ rpb_mdt->rpb_numcl = cl;
+
+ for (i = 0; i < cl; i++)
+ printf_lock("Memory cluster %d [%d - %d]\n", i,
+ rpb_mdt->rpb_cluster[i].rpb_pfn,
+ rpb_mdt->rpb_cluster[i].rpb_pfncount);
+
+ /* Checksum the rpb for good luck */
+ sum = 0;
+ lp1 = (long *)&rpb_mdt->rpb_impaddr;
+ lp2 = (long *)&rpb_mdt->rpb_cluster[cl];
+ while (lp1 < lp2) sum += *lp1++;
+ rpb_mdt->rpb_checksum = sum;
+
+ /* XXX should checksum the cluster descriptors */
+ bzero((char *)mdt_bitmap, mdt_bitmap_pages * PAGE_SIZE);
+ for (i = 0; i < mem_pages/8; i++)
+ ((unsigned char *)mdt_bitmap)[i] = 0xff;
+
+ printf_lock("Initalizing mdt_bitmap addr 0x%x mem_pages %x \n",
+ (long)mdt_bitmap,(long)mem_pages);
+
+ m5_rpb.rpb_config_off = 0;
+ m5_rpb.rpb_fru_off = 0;
+
+ rpb_dsr = (struct rpb_dsr *)((ulong)rpb_mdt + sizeof(struct _m5_rpb_mdt));
+ rpb->rpb_dsr_off = (ulong)rpb_dsr - (ulong)rpb;
+ bzero((char *)rpb_dsr, sizeof(struct rpb_dsr));
+ rpb_dsr->rpb_smm = 1578; /* Official XXM SMM number as per SRM */
+ rpb_dsr->rpb_smm = 1089; /* Official Alcor SMM number as per SRM */
+
+ rpb_lurt = (int *) ROUNDUP8((ulong)rpb_dsr + sizeof(struct rpb_dsr));
+ rpb_dsr->rpb_lurt_off = ((ulong) rpb_lurt) - (ulong) rpb_dsr;
+ bcopy((char *)m5_lurt, (char *)rpb_lurt, sizeof(m5_lurt));
+
+ rpb_name = (char *) ROUNDUP8(((ulong)rpb_lurt) + sizeof(m5_lurt));
+ rpb_dsr->rpb_sysname_off = ((ulong) rpb_name) - (ulong) rpb_dsr;
+#define THENAME " M5/Alpha "
+ sum = sizeof(THENAME);
+ bcopy(THENAME, rpb_name, sum);
+ *(ulong *)rpb_name = sizeof(THENAME); /* put in length field */
+
+ /* calculate size of rpb */
+ rpb->rpb_size = ((ulong) &rpb_name[sum]) - (ulong)rpb;
+
+ if (rpb->rpb_size > PAGE_SIZE * HWRPB_PAGES) {
+ panic("HWRPB_PAGES=%d too small for HWRPB !!! \n");
+ }
+
+ ulong *rpbptr = (ulong*)((char*)rpb_dsr + sizeof(struct rpb_dsr));
+ rpb_crb->rpb_pa_disp = KSEG_TO_PHYS(rpbptr);
+ rpb_crb->rpb_va_disp = 0x10000000 +
+ (((ulong)rpbptr - (ulong)rpb) & (0x2000 * HWRPB_PAGES - 1));
+ printf_lock("ConsoleDispatch at virt %x phys %x val %x\n",
+ rpb_crb->rpb_va_disp, rpb_crb->rpb_pa_disp, consoleCallback);
+ *rpbptr++ = 0;
+ *rpbptr++ = (ulong) consoleCallback;
+ rpb_crb->rpb_pa_fixup = KSEG_TO_PHYS(rpbptr);
+ rpb_crb->rpb_va_fixup = 0x10000000 +
+ (((ulong)rpbptr - (ulong)rpb) & (0x2000 * HWRPB_PAGES - 1));
+ *rpbptr++ = 0;
+
+ *rpbptr++ = (ulong) consoleFixup;
+
+ /* Checksum the rpb for good luck */
+ sum = 0;
+ lp1 = (long *)rpb;
+ lp2 = &rpb->rpb_checksum;
+ while (lp1 < lp2)
+ sum += *lp1++;
+ *lp2 = sum;
+
+ /*
+ * MP bootstrap
+ */
+ for (i = 1; i < m5Conf.numCPUs; i++) {
+ ulong stack = (ulong)unix_boot_alloc(1);
+ printf_lock("Bootstraping CPU %d with sp=0x%x\n", i, stack);
+ m5AlphaAccess->cpuStack[i] = stack;
+ }
+
+ /*
+ * Make sure that we are not stepping on the kernel
+ */
+ if ((ulong)unix_boot_mem >= (ulong)m5Conf.kernStart) {
+ panic("CONSOLE: too much memory. Smashing kernel\n");
+ } else {
+ printf_lock("unix_boot_mem ends at %x \n", unix_boot_mem);
+ }
+
+ JToKern((char *)bootadr, (ulong)rpb_percpu, free_pfn, kargc, kargv, NULL);
+}
+
+
+void
+JToKern(char *bootadr, ulong rpb_percpu, ulong free_pfn, ulong k_argc,
+ char **k_argv, char **envp)
+{
+ extern ulong palJToKern[];
+
+ struct _kernel_params *kernel_params = (struct _kernel_params *) KSEG;
+ int i;
+
+ printf_lock("k_argc = %d ", k_argc);
+ for (i = 0; i < k_argc; i++) {
+ printf_lock("'%s' ", k_argv[i]);
+ }
+ printf_lock("\n");
+
+ kernel_params->bootadr = bootadr;
+ kernel_params->rpb_percpu = KSEG_TO_PHYS(rpb_percpu);
+ kernel_params->free_pfn = free_pfn;
+ kernel_params->argc = k_argc;
+ kernel_params->argv = (ulong)k_argv;
+ kernel_params->envp = (ulong)envp;
+ printf_lock("jumping to kernel at 0x%x, (PCBB 0x%x pfn %d)\n",
+ bootadr, rpb_percpu, free_pfn);
+ JToPal(KSEG_TO_PHYS(palJToKern));
+ printf_lock("returned from JToPal. Looping\n");
+ while (1)
+ continue;
+}
+
+void
+JToPal(ulong bootadr)
+{
+ cServe(bootadr, 0, CSERVE_K_JTOPAL);
+
+ /*
+ * Make sure that floating point is enabled incase
+ * it was disabled by the user program.
+ */
+ wrfen(1);
+}
+
+int
+strcpy(char *dst, char *src)
+{
+ int i = 0;
+ while (*src) {
+ *dst++ = *src++;
+ i++;
+ }
+ return i;
+}
+
+/*
+ * Console I/O
+ *
+ */
+
+int numOpenDevices = 11;
+struct {
+ char name[128];
+} deviceState[32];
+
+#define BOOTDEVICE_NAME "SCSI 1 0 0 1 100 0"
+
+void
+DeviceOperation(long op, long channel, long count, long address, long block)
+{
+ long pAddr;
+
+ if (strcmp(deviceState[channel].name, BOOTDEVICE_NAME )) {
+ panic("DeviceRead: only implemented for root disk \n");
+ }
+ pAddr = KSEG_TO_PHYS(address);
+ if (pAddr + count > m5Conf.mem_size) {
+ panic("DeviceRead: request out of range \n");
+ }
+
+ m5AlphaAccess->diskCount = count;
+ m5AlphaAccess->diskPAddr = pAddr;
+ m5AlphaAccess->diskBlock = block;
+ m5AlphaAccess->diskOperation = op; /* launch */
+}
+
+/*
+ * M5 Console callbacks
+ *
+ */
+
+/* AXP manual 2-31 */
+#define CONSCB_GETC 0x1
+#define CONSCB_PUTS 0x2
+#define CONSCB_RESET_TERM 0x3
+#define CONSCB_SET_TERM_INT 0x4
+#define CONSCB_SET_TERM_CTL 0x5
+#define CONSCB_PROCESS_KEY 0x6
+#define CONSCB_OPEN_CONSOLE 0x7
+#define CONSCB_CLOSE_CONSOLE 0x8
+
+#define CONSCB_OPEN 0x10
+#define CONSCB_CLOSE 0x11
+#define CONSCB_READ 0x13
+
+#define CONSCB_GETENV 0x22
+
+/* AXP manual 2-26 */
+#define ENV_AUTO_ACTION 0X01
+#define ENV_BOOT_DEV 0X02
+#define ENV_BOOTDEF_DEV 0X03
+#define ENV_BOOTED_DEV 0X04
+#define ENV_BOOT_FILE 0X05
+#define ENV_BOOTED_FILE 0X06
+#define ENV_BOOT_OSFLAGS 0X07
+#define ENV_BOOTED_OSFLAGS 0X08
+#define ENV_BOOT_RESET 0X09
+#define ENV_DUMP_DEV 0X0A
+#define ENV_ENABLE_AUDIT 0X0B
+#define ENV_LICENSE 0X0C
+#define ENV_CHAR_SET 0X0D
+#define ENV_LANGUAGE 0X0E
+#define ENV_TTY_DEV 0X0F
+#define ENV_SCSIID 0X42
+#define ENV_SCSIFAST 0X43
+#define ENV_COM1_BAUD 0X44
+#define ENV_COM1_MODEM 0X45
+#define ENV_COM1_FLOW 0X46
+#define ENV_COM1_MISC 0X47
+#define ENV_COM2_BAUD 0X48
+#define ENV_COM2_MODEM 0X49
+#define ENV_COM2_FLOW 0X4A
+#define ENV_COM2_MISC 0X4B
+#define ENV_PASSWORD 0X4C
+#define ENV_SECURE 0X4D
+#define ENV_LOGFAIL 0X4E
+#define ENV_SRM2DEV_ID 0X4F
+
+#define MAX_ENVLEN 32
+
+char env_auto_action[MAX_ENVLEN] = "BOOT";
+char env_boot_dev[MAX_ENVLEN] = "";
+char env_bootdef_dev[MAX_ENVLEN] = "";
+char env_booted_dev[MAX_ENVLEN] = BOOTDEVICE_NAME;
+char env_boot_file[MAX_ENVLEN] = "";
+char env_booted_file[MAX_ENVLEN] = "";
+char env_boot_osflags[MAX_ENVLEN] = "";
+char env_booted_osflags[MAX_ENVLEN] = "";
+char env_boot_reset[MAX_ENVLEN] = "";
+char env_dump_dev[MAX_ENVLEN] = "";
+char env_enable_audit[MAX_ENVLEN] = "";
+char env_license[MAX_ENVLEN] = "";
+char env_char_set[MAX_ENVLEN] = "";
+char env_language[MAX_ENVLEN] = "";
+char env_tty_dev[MAX_ENVLEN] = "0";
+char env_scsiid[MAX_ENVLEN] = "";
+char env_scsifast[MAX_ENVLEN] = "";
+char env_com1_baud[MAX_ENVLEN] = "";
+char env_com1_modem[MAX_ENVLEN] = "";
+char env_com1_flow[MAX_ENVLEN] = "";
+char env_com1_misc[MAX_ENVLEN] = "";
+char env_com2_baud[MAX_ENVLEN] = "";
+char env_com2_modem[MAX_ENVLEN] = "";
+char env_com2_flow[MAX_ENVLEN] = "";
+char env_com2_misc[MAX_ENVLEN] = "";
+char env_password[MAX_ENVLEN] = "";
+char env_secure[MAX_ENVLEN] = "";
+char env_logfail[MAX_ENVLEN] = "";
+char env_srm2dev_id[MAX_ENVLEN] = "";
+
+#define MAX_ENV_INDEX 100
+char *envptr[MAX_ENV_INDEX] = {
+ 0, /* 0x00 */
+ env_auto_action, /* 0x01 */
+ env_boot_dev, /* 0x02 */
+ env_bootdef_dev, /* 0x03 */
+ env_booted_dev, /* 0x04 */
+ env_boot_file, /* 0x05 */
+ env_booted_file, /* 0x06 */
+ env_boot_osflags, /* 0x07 */
+ env_booted_osflags, /* 0x08 */
+ env_boot_reset, /* 0x09 */
+ env_dump_dev, /* 0x0A */
+ env_enable_audit, /* 0x0B */
+ env_license, /* 0x0C */
+ env_char_set, /* 0x0D */
+ (char *)&env_language, /* 0x0E */
+ env_tty_dev, /* 0x0F */
+ 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* 0x10 - 0x1F */
+ 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* 0x20 - 0x2F */
+ 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* 0x30 - 0x3F */
+ 0, /* 0x40 */
+ 0, /* 0x41 */
+ env_scsiid, /* 0x42 */
+ env_scsifast, /* 0x43 */
+ env_com1_baud, /* 0x44 */
+ env_com1_modem, /* 0x45 */
+ env_com1_flow, /* 0x46 */
+ env_com1_misc, /* 0x47 */
+ env_com2_baud, /* 0x48 */
+ env_com2_modem, /* 0x49 */
+ env_com2_flow, /* 0x4A */
+ env_com2_misc, /* 0x4B */
+ env_password, /* 0x4C */
+ env_secure, /* 0x4D */
+ env_logfail, /* 0x4E */
+ env_srm2dev_id, /* 0x4F */
+ 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, /* 0x50 - 0x5F */
+ 0, /* 0x60 */
+ 0, /* 0x61 */
+ 0, /* 0x62 */
+ 0, /* 0x63 */
+};
+
+long
+CallBackDispatcher(long a0, long a1, long a2, long a3, long a4)
+{
+ long i;
+ switch (a0) {
+ case CONSCB_GETC:
+ return GetChar();
+
+ case CONSCB_PUTS:
+ for (i = 0; i < a3; i++)
+ PutChar(*((char *)a2 + i));
+ return a3;
+
+ case CONSCB_GETENV:
+ if (a1 >= 0 && a1 < MAX_ENV_INDEX && envptr[a1] != 0 && *envptr[a1]) {
+ i = strcpy((char*)a2, envptr[a1]);
+ } else {
+ strcpy((char*)a2, "");
+ i = (long)0xc000000000000000;
+ if (a1 >= 0 && a1 < MAX_ENV_INDEX)
+ printf_lock("GETENV unsupported option %d (0x%x)\n", a1, a1);
+ else
+ printf_lock("GETENV unsupported option %s\n", a1);
+ }
+
+ if (i > a3)
+ panic("CONSCB_GETENV overwrote buffer\n");
+ return i;
+
+ case CONSCB_OPEN:
+ bcopy((char*)a1, deviceState[numOpenDevices].name, a2);
+ deviceState[numOpenDevices].name[a2] = '\0';
+ printf_lock("CONSOLE OPEN : %s --> success \n",
+ deviceState[numOpenDevices].name);
+ return numOpenDevices++;
+
+ case CONSCB_READ:
+ DeviceOperation(a0, a1, a2, a3, a4);
+ break;
+
+ case CONSCB_CLOSE:
+ break;
+
+ case CONSCB_OPEN_CONSOLE:
+ printf_lock("CONSOLE OPEN\n");
+ return 0; /* success */
+ break; /* not reached */
+
+ case CONSCB_CLOSE_CONSOLE:
+ printf_lock("CONSOLE CLOSE\n");
+ return 0; /* success */
+ break; /* not reached */
+
+ default:
+ panic("CallBackDispatcher(%x,%x,%x,%x,%x)\n", a0, a1, a2, a3, a4);
+ }
+
+ return 0;
+}
+
+long
+CallBackFixup(int a0, int a1, int a2)
+{
+ long temp;
+ /*
+ * Linux uses r8 for the current pointer (pointer to data
+ * structure contating info about currently running process). It
+ * is set when the kernel starts and is expected to remain
+ * there... Problem is that the unlike the kernel, the console
+ * does not prevent the assembler from using r8. So here is a work
+ * around. So far this has only been a problem in CallBackFixup()
+ * but any other call back functions couldd cause a problem at
+ * some point
+ */
+
+ /* save off the current pointer to a temp variable */
+ asm("bis $8, $31, %0" : "=r" (temp));
+
+ /* call original code */
+ printf_lock("CallbackFixup %x %x, t7=%x\n", a0, a1, temp);
+
+ /* restore the current pointer */
+ asm("bis %0, $31, $8" : : "r" (temp) : "$8");
+
+ return 0;
+}
+
+void
+SlaveCmd(int cpu, struct rpb_percpu *my_rpb)
+{
+ extern ulong palJToSlave[];
+
+ printf_lock("Slave CPU %d console command %s", cpu,
+ my_rpb->rpb_iccb.iccb_rxbuf);
+
+ my_rpb->rpb_state |= STATE_BIP;
+ my_rpb->rpb_state &= ~STATE_RC;
+
+ printf_lock("SlaveCmd: restart %x %x vptb %x my_rpb %x my_rpb_phys %x\n",
+ rpb->rpb_restart, rpb->rpb_restart_pv, rpb->rpb_vptb, my_rpb,
+ KSEG_TO_PHYS(my_rpb));
+
+ cServe(KSEG_TO_PHYS(palJToSlave), (ulong)rpb->rpb_restart,
+ CSERVE_K_JTOPAL, rpb->rpb_restart_pv, rpb->rpb_vptb,
+ KSEG_TO_PHYS(my_rpb));
+
+ panic("SlaveCmd returned \n");
+}
+
+void
+SlaveLoop(int cpu)
+{
+ int size = ROUNDUP128(sizeof(struct rpb_percpu));
+ struct rpb_percpu *my_rpb = (struct rpb_percpu*)
+ ((ulong)rpb_percpu + size * cpu);
+
+ if (cpu == 0) {
+ panic("CPU 0 entering slaveLoop. Reenetering the console. HOSED\n");
+ } else {
+ printf_lock("Entering slaveloop for cpu %d my_rpb=%x\n", cpu, my_rpb);
+ }
+
+ // swap the processors context to the one in the
+ // rpb_percpu struct very carefully (i.e. no stack usage)
+ // so that linux knows which processor ends up in __smp_callin
+ // and we don't trash any data is the process
+ SlaveSpin(cpu, my_rpb, &my_rpb->rpb_iccb.iccb_rxlen);
+}
diff --git a/system/alpha/console/dbmentry.S b/system/alpha/console/dbmentry.S
new file mode 100644
index 000000000..56a2c1950
--- /dev/null
+++ b/system/alpha/console/dbmentry.S
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Debug Monitor Entry code
+ */
+#include "fromHudsonOsf.h"
+
+ .extern myAlphaAccess
+ .text
+
+/* return address and padding to octaword align */
+#define STARTFRM 16
+
+ .globl _start
+ .ent _start, 0
+_start:
+_entry:
+ br t0, 2f # get the current PC
+2: ldgp gp, 0(t0) # init gp
+
+/* Processor 0 start stack frame is begining of physical memory (0)
+ Other processors spin here waiting to get their stacks from
+ Processor 0, then they can progress as normal.
+*/
+ call_pal PAL_WHAMI_ENTRY
+ beq v0, cpuz
+ ldq t3, m5AlphaAccess
+ addq t3,0x70,t3 # *** If offset in console alpha access struct changes
+ # This must be changed as well!
+ bis zero,8,t4
+ mulq t4,v0,t4
+ addq t3,t4,t3
+ ldah a0, 3(zero) # load arg0 with 65536*3
+cpuwait: .long 0x6000002 # jsr quiesceNs
+ ldq t4, 0(t3)
+ beq t4, cpuwait
+ bis t4,t4,sp
+
+
+cpuz: bis sp,sp,s0 /* save sp */
+
+slave: lda v0,(8*1024)(sp) /* end of page */
+
+ subq zero, 1, t0
+ sll t0, 42, t0
+ bis t0, v0, sp
+
+ lda sp, -STARTFRM(sp) # Create a stack frame
+ stq ra, 0(sp) # Place return address on the stack
+
+ .mask 0x84000000, -8
+ .frame sp, STARTFRM, ra
+
+/*
+ * Enable the Floating Point Unit
+ */
+ lda a0, 1(zero)
+ call_pal PAL_WRFEN_ENTRY
+
+/*
+ * Every good C program has a main()
+ */
+
+/* If stack pointer was 0, then this is CPU0*/
+ beq s0,master
+
+ call_pal PAL_WHAMI_ENTRY
+ bis v0,v0,a0
+ jsr ra, SlaveLoop
+master:
+ jsr ra, main
+
+
+
+/*
+ * The Debug Monitor should never return.
+ * However, just incase...
+ */
+ ldgp gp, 0(ra)
+ bsr zero, _exit
+
+.end _start
+
+
+
+ .globl _exit
+ .ent _exit, 0
+_exit:
+
+ ldq ra, 0(sp) # restore return address
+ lda sp, STARTFRM(sp) # prune back the stack
+ ret zero, (ra) # Back from whence we came
+.end _exit
+
+ .globl cServe
+ .ent cServe 2
+cServe:
+ .option O1
+ .frame sp, 0, ra
+ call_pal PAL_CSERVE_ENTRY
+ ret zero, (ra)
+ .end cServe
+
+ .globl wrfen
+ .ent wrfen 2
+wrfen:
+ .option O1
+ .frame sp, 0, ra
+ call_pal PAL_WRFEN_ENTRY
+ ret zero, (ra)
+ .end wrfen
+ .globl consoleCallback
+ .ent consoleCallback 2
+consoleCallback:
+ br t0, 2f # get the current PC
+2: ldgp gp, 0(t0) # init gp
+ lda sp,-64(sp)
+ stq ra,0(sp)
+ jsr CallBackDispatcher
+ ldq ra,0(sp)
+ lda sp,64(sp)
+ ret zero,(ra)
+ .end consoleCallback
+
+
+ .globl consoleFixup
+ .ent consoleFixup 2
+consoleFixup:
+ br t0, 2f # get the current PC
+2: ldgp gp, 0(t0) # init gp
+ lda sp,-64(sp)
+ stq ra,0(sp)
+ jsr CallBackFixup
+ ldq ra,0(sp)
+ lda sp,64(sp)
+ ret zero,(ra)
+ .end consoleFixup
+
+
+
+ .globl SpinLock
+ .ent SpinLock 2
+SpinLock:
+1:
+ ldq_l a1,0(a0) # interlock complete lock state
+ subl ra,3,v0 # get calling addr[31:0] + 1
+ blbs a1,2f # branch if lock is busy
+ stq_c v0,0(a0) # attempt to acquire lock
+ beq v0,2f # branch if lost atomicity
+ mb # ensure memory coherence
+ ret zero,(ra) # return to caller (v0 is 1)
+2:
+ br zero,1b
+ .end SpinLock
+
+ .globl loadContext
+ .ent loadContext 2
+loadContext:
+ .option O1
+ .frame sp, 0, ra
+ call_pal PAL_SWPCTX_ENTRY
+ ret zero, (ra)
+ .end loadContext
+
+
+ .globl SlaveSpin # Very carefully spin wait
+ .ent SlaveSpin 2 # and swap context without
+SlaveSpin: # using any stack space
+ .option O1
+ .frame sp, 0, ra
+ mov a0, t0 # cpu number
+ mov a1, t1 # cpu rpb pointer (virtual)
+ mov a2, t2 # what to spin on
+ ldah a0, 3(zero) # load arg0 with 65536
+test: .long 0x6000002 # jsr quiesceNs # wait 65us*3
+ ldl t3, 0(t2)
+ beq t3, test
+ zapnot t1,0x1f,a0 # make rpb physical
+ call_pal PAL_SWPCTX_ENTRY # switch to pcb
+ mov t0, a0 # setup args for SlaveCmd
+ mov t1, a1
+ jsr SlaveCmd # call SlaveCmd
+ ret zero, (ra) # Should never be reached
+ .end SlaveSpin
+
+
diff --git a/system/alpha/console/paljtokern.S b/system/alpha/console/paljtokern.S
new file mode 100644
index 000000000..dfaf32533
--- /dev/null
+++ b/system/alpha/console/paljtokern.S
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
+#include "ev5_defs.h"
+#include "fromHudsonOsf.h" // OSF/1 specific definitions
+#include "fromHudsonMacros.h" // Global macro definitions
+
+/* Jump to kernel
+ * args:
+ * Kernel address - a0
+ * PCBB - a1
+ * First free PFN - a3?
+ *
+ * Enable kseg addressing in ICSR
+ * Enable kseg addressing in MCSR
+ * Set VTBR -- Set to 1GB as per SRM, or maybe 8GB??
+ * Set PCBB -- pass pointer in arg
+ * Set PTBR -- get it out of PCB
+ * Set KSP -- get it out of PCB
+ *
+ * Jump to kernel address
+ *
+ * Kernel args-
+ * s0 first free PFN
+ * s1 ptbr
+ * s2 argc 0
+ * s3 argv NULL
+ * s5 osf_param (sysconfigtab) NULL
+ */
+
+ .global palJToKern
+ .text 3
+palJToKern:
+ ALIGN_BRANCH
+
+ ldq_p a0, 0(zero)
+ ldq_p a1, 8(zero)
+ ldq_p a3, 16(zero)
+
+ /* Point the Vptbr at 8GB */
+ lda t0, 0x1(zero)
+ sll t0, 33, t0
+
+ mtpr t0, mVptBr // Load Mbox copy
+ mtpr t0, iVptBr // Load Ibox copy
+ STALL // don't dual issue the load with mtpr -pb
+
+ /* Turn on superpage mapping in the mbox and icsr */
+ lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
+ STALL // don't dual issue the load with mtpr -pb
+ mtpr t0, mcsr // Set the super page mode enable bit
+ STALL // don't dual issue the load with mtpr -pb
+
+ lda t0, 0(zero)
+ mtpr t0, dtbAsn
+ mtpr t0, itbAsn
+
+ LDLI (t1,0x20000000)
+ STALL // don't dual issue the load with mtpr -pb
+ mfpr t0, icsr // Enable superpage mapping
+ STALL // don't dual issue the load with mtpr -pb
+ bis t0, t1, t0
+ mtpr t0, icsr
+
+ STALL // Required stall to update chip ...
+ STALL
+ STALL
+ STALL
+ STALL
+
+ ldq_p s0, PCB_Q_PTBR(a1)
+ sll s0, VA_S_OFF, s0 // Shift PTBR into position
+ STALL // don't dual issue the load with mtpr -pb
+ mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
+ STALL // don't dual issue the load with mtpr -pb
+ ldq_p sp, PCB_Q_KSP(a1)
+
+ mtpr a0, excAddr // Load the dispatch address.
+ STALL // don't dual issue the load with mtpr -pb
+ bis a3, zero, a0 // first free PFN
+ ldq_p a1, PCB_Q_PTBR(a1) // ptbr
+ ldq_p a2, 24(zero) // argc
+ ldq_p a3, 32(zero) // argv
+ ldq_p a4, 40(zero) // environ
+ lda a5, 0(zero) // osf_param
+ STALL // don't dual issue the load with mtpr -pb
+ mtpr zero, dtbIa // Flush all D-stream TB entries
+ mtpr zero, itbIa // Flush all I-stream TB entries
+ br zero, 2f
+
+ ALIGN_BLOCK
+
+2: NOP
+ mtpr zero, icFlush // Flush the icache.
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 1-10
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 11-20
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 21-30
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 31-40
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 41-44
+ NOP
+ NOP
+ NOP
+
+ hw_rei_stall // Dispatch to kernel
diff --git a/system/alpha/console/paljtoslave.S b/system/alpha/console/paljtoslave.S
new file mode 100644
index 000000000..59cfb210d
--- /dev/null
+++ b/system/alpha/console/paljtoslave.S
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "dc21164FromGasSources.h" // DECchip 21164 specific definitions
+#include "ev5_defs.h"
+#include "fromHudsonOsf.h" // OSF/1 specific definitions
+#include "fromHudsonMacros.h" // Global macro definitions
+
+/*
+ * args:
+ * a0: here
+ * a1: boot location
+ * a2: CSERVE_J_KTOPAL
+ * a3: restrart_pv
+ * a4: vptb
+ * a5: my_rpb
+ *
+ * SRM Console Architecture III 3-26
+ */
+
+ .global palJToSlave
+ .text 3
+palJToSlave:
+
+ ALIGN_BRANCH
+
+ bis a3, zero, pv
+ bis zero, zero, t11
+ bis zero, zero, ra
+
+ /* Point the Vptbr to a2 */
+
+ mtpr a4, mVptBr // Load Mbox copy
+ mtpr a4, iVptBr // Load Ibox copy
+ STALL // don't dual issue the load with mtpr -pb
+
+ /* Turn on superpage mapping in the mbox and icsr */
+ lda t0, (2<<MCSR_V_SP)(zero) // Get a '10' (binary) in MCSR<SP>
+ STALL // don't dual issue the load with mtpr -pb
+ mtpr t0, mcsr // Set the super page mode enable bit
+ STALL // don't dual issue the load with mtpr -pb
+
+ lda t0, 0(zero)
+ mtpr t0, dtbAsn
+ mtpr t0, itbAsn
+
+ LDLI (t1,0x20000000)
+ STALL // don't dual issue the load with mtpr -pb
+ mfpr t0, icsr // Enable superpage mapping
+ STALL // don't dual issue the load with mtpr -pb
+ bis t0, t1, t0
+ mtpr t0, icsr
+
+ STALL // Required stall to update chip ...
+ STALL
+ STALL
+ STALL
+ STALL
+
+ ldq_p s0, PCB_Q_PTBR(a5)
+ sll s0, VA_S_OFF, s0 // Shift PTBR into position
+ STALL // don't dual issue the load with mtpr -pb
+ mtpr s0, ptPtbr // PHYSICAL MBOX INST -> MT PT20 IN 0,1
+ STALL // don't dual issue the load with mtpr -pb
+ ldq_p sp, PCB_Q_KSP(a5)
+
+ mtpr zero, dtbIa // Flush all D-stream TB entries
+ mtpr zero, itbIa // Flush all I-stream TB entries
+
+ mtpr a1, excAddr // Load the dispatch address.
+
+ STALL // don't dual issue the load with mtpr -pb
+ STALL // don't dual issue the load with mtpr -pb
+ mtpr zero, dtbIa // Flush all D-stream TB entries
+ mtpr zero, itbIa // Flush all I-stream TB entries
+ br zero, 2f
+
+ ALIGN_BLOCK
+
+2: NOP
+ mtpr zero, icFlush // Flush the icache.
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 1-10
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 11-20
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 21-30
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 31-40
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+ NOP
+
+ NOP // Required NOPs ... 41-44
+ NOP
+ NOP
+ NOP
+
+ hw_rei_stall // Dispatch to kernel
+
diff --git a/system/alpha/console/printf.c b/system/alpha/console/printf.c
new file mode 100644
index 000000000..3d8cb4108
--- /dev/null
+++ b/system/alpha/console/printf.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2003-2004 The Regents of The University of Michigan
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/types.h>
+#include <stdarg.h>
+#include <stdint.h>
+#include "m5op.h"
+
+/* The string s is terminated by a '\0' */
+void
+PutString(const char *s)
+{
+ while (*s)
+ PutChar(*s++);
+}
+
+/* print c count times */
+void
+PutRepChar(char c, int count)
+{
+ while (count--)
+ PutChar(c);
+}
+
+/* put string reverse */
+void
+PutStringReverse(const char *s, int index)
+{
+ while (index-- > 0)
+ PutChar(s[index]);
+}
+
+/*
+ * prints value in radix, in a field width width, with fill
+ * character fill
+ * if radix is negative, print as signed quantity
+ * if width is negative, left justify
+ * if width is 0, use whatever is needed
+ * if fill is 0, use ' '
+ */
+void
+PutNumber(long value, int radix, int width, char fill)
+{
+ char buffer[40];
+ uint bufferindex = 0;
+ ulong uvalue;
+ ushort digit;
+ ushort left = 0;
+ ushort negative = 0;
+
+ if (fill == 0)
+ fill = ' ';
+
+ if (width < 0) {
+ width = -width;
+ left = 1;
+ }
+
+ if (width < 0 || width > 80)
+ width = 0;
+
+ if (radix < 0) {
+ radix = -radix;
+ if (value < 0) {
+ negative = 1;
+ value = -value;
+ }
+ }
+
+ switch (radix) {
+ case 8:
+ case 10:
+ case 16:
+ break;
+
+ default:
+ PutString("****");
+ return;
+ }
+
+ uvalue = value;
+
+ do {
+ if (radix != 16) {
+ digit = (ushort)(uvalue % radix);
+ uvalue /= radix;
+ } else {
+ digit = (ushort)(uvalue & 0xf);
+ uvalue = uvalue >> 4;
+ }
+ buffer[bufferindex] = digit + ((digit <= 9) ? '0' : ('A' - 10));
+ bufferindex += 1;
+ } while (uvalue != 0);
+
+ /* fill # ' ' and negative cannot happen at once */
+ if (negative) {
+ buffer[bufferindex] = '-';
+ bufferindex += 1;
+ }
+
+ if ((uint)width <= bufferindex) {
+ PutStringReverse(buffer, bufferindex);
+ } else {
+ width -= bufferindex;
+ if (!left)
+ PutRepChar(fill, width);
+ PutStringReverse(buffer, bufferindex);
+ if (left)
+ PutRepChar(fill, width);
+ }
+}
+
+ulong
+power(long base, long n)
+{
+ ulong p;
+
+ for (p = 1; n > 0; --n)
+ p = p * base;
+ return p;
+}
+
+void
+putFloat(double a, int fieldwidth, char fill)
+{
+ int i;
+ ulong b;
+
+ /*
+ * Put out everything before the decimal place.
+ */
+ PutNumber(((ulong) a), 10, fieldwidth, fill);
+
+ /*
+ * Output the decimal place.
+ */
+ PutChar('.' & 0x7f);
+
+ /*
+ * Output the n digits after the decimal place.
+ */
+ for (i = 1; i < 6; i++) {
+ b = (ulong)(power(10, i) * (double)(a - (ulong) a));
+ PutChar((char)(b % 10) + '0');
+ }
+}
+
+const char *
+FormatItem(const char *f, va_list *ap)
+{
+ char c;
+ int fieldwidth = 0;
+ int leftjust = 0;
+ int radix = 0;
+ char fill = ' ';
+
+ if (*f == '0')
+ fill = '0';
+
+ while (c = *f++) {
+ if (c >= '0' && c <= '9') {
+ fieldwidth = (fieldwidth * 10) + (c - '0');
+ } else {
+ switch (c) {
+ case '\000':
+ return(--f);
+ case '%':
+ PutChar('%');
+ return(f);
+ case '-':
+ leftjust = 1;
+ break;
+ case 'c': {
+ char a = (char)va_arg(*ap, int);
+
+ if (leftjust)
+ PutChar(a & 0x7f);
+ if (fieldwidth > 0)
+ PutRepChar(fill, fieldwidth - 1);
+ if (!leftjust)
+ PutChar(a & 0x7f);
+ return(f);
+ }
+ case 's': {
+ const char *a = va_arg(*ap, const char *);
+
+ if (leftjust)
+ PutString((const char *) a);
+ if (fieldwidth > strlen((const char *) a))
+ PutRepChar(fill, fieldwidth - strlen((const char *)a));
+ if (!leftjust)
+ PutString((const char *) a);
+ return(f);
+ }
+ case 'd':
+ radix = -10;
+ break;
+ case 'u':
+ radix = 10;
+ break;
+ case 'x':
+ radix = 16;
+ break;
+ case 'X':
+ radix = 16;
+ break;
+ case 'o':
+ radix = 8;
+ break;
+ case 'f': {
+ double a = va_arg(*ap, double);
+
+ putFloat(a, fieldwidth, fill);
+ return(f);
+ }
+ default: /* unknown switch! */
+ radix = 3;
+ break;
+ }
+ }
+
+ if (radix)
+ break;
+ }
+
+ if (leftjust)
+ fieldwidth = -fieldwidth;
+
+ long a = va_arg(*ap, long);
+ PutNumber(a, radix, fieldwidth, fill);
+
+ return(f);
+}
+
+int
+printf(const char *f, ...)
+{
+ va_list ap;
+
+ va_start(ap, f);
+
+ while (*f) {
+ if (*f == '%')
+ f = FormatItem(f + 1, &ap);
+ else
+ PutChar(*f++);
+ }
+
+ if (*(f - 1) == '\n') {
+ /* add a line-feed (SimOS console output goes to shell */
+ PutChar('\r');
+ }
+
+ va_end(ap); /* clean up */
+ return 0;
+}
+
+void
+panic(const char *f, ...)
+{
+ va_list ap;
+
+ va_start(ap, f);
+
+ printf("CONSOLE PANIC (looping): ");
+ while (*f) {
+ if (*f == '%')
+ f = FormatItem(f + 1, &ap);
+ else
+ PutChar(*f++);
+ }
+
+ va_end(ap); /* clean up */
+ m5_panic();
+}
diff --git a/system/alpha/h/cserve.h b/system/alpha/h/cserve.h
new file mode 100644
index 000000000..5b0e0f61c
--- /dev/null
+++ b/system/alpha/h/cserve.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define __CSERVE_LOADED 1
+
+/*
+ * Console Service (cserve) sub-function codes:
+ */
+#define CSERVE_K_LDQP 0x01
+#define CSERVE_K_STQP 0x02
+#define CSERVE_K_JTOPAL 0x09
+#define CSERVE_K_WR_INT 0x0A
+#define CSERVE_K_RD_IMPURE 0x0B
+#define CSERVE_K_PUTC 0x0F
+#define CSERVE_K_WR_ICSR 0x10
+#define CSERVE_K_WR_ICCSR 0x10 /* for ev4 backwards compatibility */
+#define CSERVE_K_RD_ICSR 0x11
+#define CSERVE_K_RD_ICCSR 0x11 /* for ev4 backwards compatibility */
+#define CSERVE_K_RD_BCCTL 0x12
+#define CSERVE_K_RD_BCCFG 0x13
+
+#define CSERVE_K_WR_BCACHE 0x16
+
+#define CSERVE_K_RD_BCCFG_OFF 0x17
+#define CSERVE_K_JTOKERN 0x18
+
+
diff --git a/system/alpha/h/dc21164FromGasSources.h b/system/alpha/h/dc21164FromGasSources.h
new file mode 100644
index 000000000..038861d36
--- /dev/null
+++ b/system/alpha/h/dc21164FromGasSources.h
@@ -0,0 +1,886 @@
+/*
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DC21164FROMGASSOURCES_INCLUDED
+#define DC21164FROMGASSOURCES_INCLUDED 1
+
+/*
+**
+** INTERNAL PROCESSOR REGISTER DEFINITIONS
+**
+** The internal processor register definitions below are annotated
+** with one of the following symbols:
+**
+** RW - The register may be read and written
+** RO - The register may only be read
+** WO - The register may only be written
+**
+** For RO and WO registers, all bits and fields within the register are
+** also read-only or write-only. For RW registers, each bit or field
+** within the register is annotated with one of the following:
+**
+** RW - The bit/field may be read and written
+** RO - The bit/field may be read; writes are ignored
+** WO - The bit/field may be written; reads return UNPREDICTABLE
+** WZ - The bit/field may be written; reads return a zero value
+** W0C - The bit/field may be read; write-zero-to-clear
+** W1C - The bit/field may be read; write-one-to-clear
+** WA - The bit/field may be read; write-anything-to-clear
+** RC - The bit/field may be read, causing state to clear;
+** writes are ignored
+**
+*/
+
+
+/*
+**
+** Ibox IPR Definitions:
+**
+*/
+
+// replaced by ev5_defs.h #define isr 0x100 /* RO - Interrupt Summary */
+#define itbTag 0x101 /* WO - ITB Tag */
+#define itbPte 0x102 /* RW - ITB Page Table Entry */
+#define itbAsn 0x103 /* RW - ITB Address Space Number */
+#define itbPteTemp 0x104 /* RO - ITB Page Table Entry Temporary */
+#define itbIa 0x105 /* WO - ITB Invalidate All */
+#define itbIap 0x106 /* WO - ITB Invalidate All Process */
+#define itbIs 0x107 /* WO - ITB Invalidate Single */
+// replaced by ev5_defs.h #define sirr 0x108 /* RW - Software Interrupt Request */
+// replaced by ev5_defs.h #define astrr 0x109 /* RW - Async. System Trap Request */
+// replaced by ev5_defs.h #define aster 0x10A /* RW - Async. System Trap Enable */
+#define excAddr 0x10B /* RW - Exception Address */
+#define excSum 0x10C /* RW - Exception Summary */
+#define excMask 0x10D /* RO - Exception Mask */
+#define palBase 0x10E /* RW - PAL Base */
+#define ips 0x10F /* RW - Processor Status */
+// replaced by ev5_defs.h #define ipl 0x110 /* RW - Interrupt Priority Level */
+#define intId 0x111 /* RO - Interrupt ID */
+#define iFaultVaForm 0x112 /* RO - Formatted Faulting VA */
+#define iVptBr 0x113 /* RW - I-Stream Virtual Page Table Base */
+#define hwIntClr 0x115 /* WO - Hardware Interrupt Clear */
+#define slXmit 0x116 /* WO - Serial Line Transmit */
+#define slRcv 0x117 /* RO - Serial Line Receive */
+// replaced by ev5_defs.h #define icsr 0x118 /* RW - Ibox Control/Status */
+#define icFlush 0x119 /* WO - I-Cache Flush Control */
+#define flushIc 0x119 /* WO - I-Cache Flush Control (DC21064 Symbol) */
+#define icPerr 0x11A /* RW - I-Cache Parity Error Status */
+#define PmCtr 0x11C /* RW - Performance Counter */
+
+/*
+**
+** Ibox Control/Status Register (ICSR) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ------------------------------------
+** <39> 1 TST RW,0 Assert Test Status
+** <38> 1 ISTA RO I-Cache BIST Status
+** <37> 1 DBS RW,1 Debug Port Select
+** <36> 1 FBD RW,0 Force Bad I-Cache Data Parity
+** <35> 1 FBT RW,0 Force Bad I-Cache Tag Parity
+** <34> 1 FMS RW,0 Force I-Cache Miss
+** <33> 1 SLE RW,0 Enable Serial Line Interrupts
+** <32> 1 CRDE RW,0 Enable Correctable Error Interrupts
+** <30> 1 SDE RW,0 Enable PAL Shadow Registers
+** <29:28> 2 SPE RW,0 Enable I-Stream Super Page Mode
+** <27> 1 HWE RW,0 Enable PALRES Instrs in Kernel Mode
+** <26> 1 FPE RW,0 Enable Floating Point Instructions
+** <25> 1 TMD RW,0 Disable Ibox Timeout Counter
+** <24> 1 TMM RW,0 Timeout Counter Mode
+**
+*/
+
+#define ICSR_V_TST 39
+#define ICSR_M_TST (1<<ICSR_V_TST)
+#define ICSR_V_ISTA 38
+#define ICSR_M_ISTA (1<<ICSR_V_ISTA)
+#define ICSR_V_DBS 37
+#define ICSR_M_DBS (1<<ICSR_V_DBS)
+#define ICSR_V_FBD 36
+#define ICSR_M_FBD (1<<ICSR_V_FBD)
+#define ICSR_V_FBT 35
+#define ICSR_M_FBT (1<<ICSR_V_FBT)
+#define ICSR_V_FMS 34
+#define ICSR_M_FMS (1<<ICSR_V_FMS)
+#define ICSR_V_SLE 33
+#define ICSR_M_SLE (1<<ICSR_V_SLE)
+#define ICSR_V_CRDE 32
+#define ICSR_M_CRDE (1<<ICSR_V_CRDE)
+#define ICSR_V_SDE 30
+#define ICSR_M_SDE (1<<ICSR_V_SDE)
+#define ICSR_V_SPE 28
+#define ICSR_M_SPE (3<<ICSR_V_SPE)
+#define ICSR_V_HWE 27
+#define ICSR_M_HWE (1<<ICSR_V_HWE)
+#define ICSR_V_FPE 26
+#define ICSR_M_FPE (1<<ICSR_V_FPE)
+#define ICSR_V_TMD 25
+#define ICSR_M_TMD (1<<ICSR_V_TMD)
+#define ICSR_V_TMM 24
+#define ICSR_M_TMM (1<<ICSR_V_TMM)
+
+/*
+**
+** Serial Line Tranmit Register (SL_XMIT)
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ------------------------------------
+** <7> 1 TMT WO,1 Serial line transmit data
+**
+*/
+
+#define SLXMIT_V_TMT 7
+#define SLXMIT_M_TMT (1<<SLXMIT_V_TMT)
+
+/*
+**
+** Serial Line Receive Register (SL_RCV)
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ------------------------------------
+** <6> 1 RCV RO Serial line receive data
+**
+*/
+
+#define SLRCV_V_RCV 6
+#define SLRCV_M_RCV (1<<SLRCV_V_RCV)
+
+/*
+**
+** Icache Parity Error Status Register (ICPERR) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ------------------------------------
+** <13> 1 TMR W1C Timeout reset error
+** <12> 1 TPE W1C Tag parity error
+** <11> 1 DPE W1C Data parity error
+**
+*/
+
+#define ICPERR_V_TMR 13
+#define ICPERR_M_TMR (1<<ICPERR_V_TMR)
+#define ICPERR_V_TPE 12
+#define ICPERR_M_TPE (1<<ICPERR_V_TPE)
+#define ICPERR_V_DPE 11
+#define ICPERR_M_DPE (1<<ICPERR_V_DPE)
+
+#define ICPERR_M_ALL (ICPERR_M_TMR | ICPERR_M_TPE | ICPERR_M_DPE)
+
+/*
+**
+** Exception Summary Register (EXC_SUM) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ------------------------------------
+** <16> 1 IOV WA Integer overflow
+** <15> 1 INE WA Inexact result
+** <14> 1 UNF WA Underflow
+** <13> 1 FOV WA Overflow
+** <12> 1 DZE WA Division by zero
+** <11> 1 INV WA Invalid operation
+** <10> 1 SWC WA Software completion
+**
+*/
+
+#define EXC_V_IOV 16
+#define EXC_M_IOV (1<<EXC_V_IOV)
+#define EXC_V_INE 15
+#define EXC_M_INE (1<<EXC_V_INE)
+#define EXC_V_UNF 14
+#define EXC_M_UNF (1<<EXC_V_UNF)
+#define EXC_V_FOV 13
+#define EXC_M_FOV (1<<EXC_V_FOV)
+#define EXC_V_DZE 12
+#define EXC_M_DZE (1<<EXC_V_DZE)
+#define EXC_V_INV 11
+#define EXC_M_INV (1<<EXC_V_INV)
+#define EXC_V_SWC 10
+#define EXC_M_SWC (1<<EXC_V_SWC)
+
+/*
+**
+** Hardware Interrupt Clear Register (HWINT_CLR) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ---------------------------------
+** <33> 1 SLC W1C Clear Serial Line interrupt
+** <32> 1 CRDC W1C Clear Correctable Read Data interrupt
+** <29> 1 PC2C W1C Clear Performance Counter 2 interrupt
+** <28> 1 PC1C W1C Clear Performance Counter 1 interrupt
+** <27> 1 PC0C W1C Clear Performance Counter 0 interrupt
+**
+*/
+
+#define HWINT_V_SLC 33
+#define HWINT_M_SLC (1<<HWINT_V_SLC)
+#define HWINT_V_CRDC 32
+#define HWINT_M_CRDC (1<<HWINT_V_CRDC)
+#define HWINT_V_PC2C 29
+#define HWINT_M_PC2C (1<<HWINT_V_PC2C)
+#define HWINT_V_PC1C 28
+#define HWINT_M_PC1C (1<<HWINT_V_PC1C)
+#define HWINT_V_PC0C 27
+#define HWINT_M_PC0C (1<<HWINT_V_PC0C)
+
+/*
+**
+** Interrupt Summary Register (ISR) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ---------------------------------
+** <34> 1 HLT RO External Halt interrupt
+** <33> 1 SLI RO Serial Line interrupt
+** <32> 1 CRD RO Correctable ECC errors
+** <31> 1 MCK RO System Machine Check
+** <30> 1 PFL RO Power Fail
+** <29> 1 PC2 RO Performance Counter 2 interrupt
+** <28> 1 PC1 RO Performance Counter 1 interrupt
+** <27> 1 PC0 RO Performance Counter 0 interrupt
+** <23> 1 I23 RO External Hardware interrupt
+** <22> 1 I22 RO External Hardware interrupt
+** <21> 1 I21 RO External Hardware interrupt
+** <20> 1 I20 RO External Hardware interrupt
+** <19> 1 ATR RO Async. System Trap request
+** <18:4> 15 SIRR RO,0 Software Interrupt request
+** <3:0> 4 ASTRR RO Async. System Trap request (USEK)
+**
+**/
+
+#define ISR_V_HLT 34
+#define ISR_M_HLT (1<<ISR_V_HLT)
+#define ISR_V_SLI 33
+#define ISR_M_SLI (1<<ISR_V_SLI)
+#define ISR_V_CRD 32
+#define ISR_M_CRD (1<<ISR_V_CRD)
+#define ISR_V_MCK 31
+#define ISR_M_MCK (1<<ISR_V_MCK)
+#define ISR_V_PFL 30
+#define ISR_M_PFL (1<<ISR_V_PFL)
+#define ISR_V_PC2 29
+#define ISR_M_PC2 (1<<ISR_V_PC2)
+#define ISR_V_PC1 28
+#define ISR_M_PC1 (1<<ISR_V_PC1)
+#define ISR_V_PC0 27
+#define ISR_M_PC0 (1<<ISR_V_PC0)
+#define ISR_V_I23 23
+#define ISR_M_I23 (1<<ISR_V_I23)
+#define ISR_V_I22 22
+#define ISR_M_I22 (1<<ISR_V_I22)
+#define ISR_V_I21 21
+#define ISR_M_I21 (1<<ISR_V_I21)
+#define ISR_V_I20 20
+#define ISR_M_I20 (1<<ISR_V_I20)
+#define ISR_V_ATR 19
+#define ISR_M_ATR (1<<ISR_V_ATR)
+#define ISR_V_SIRR 4
+#define ISR_M_SIRR (0x7FFF<<ISR_V_SIRR)
+#define ISR_V_ASTRR 0
+#define ISR_M_ASTRR (0xF<<ISR_V_ASTRR)
+
+/*
+**
+** Mbox and D-Cache IPR Definitions:
+**
+*/
+
+#define dtbAsn 0x200 /* WO - DTB Address Space Number */
+#define dtbCm 0x201 /* WO - DTB Current Mode */
+#define dtbTag 0x202 /* WO - DTB Tag */
+#define dtbPte 0x203 /* RW - DTB Page Table Entry */
+#define dtbPteTemp 0x204 /* RO - DTB Page Table Entry Temporary */
+#define mmStat 0x205 /* RO - D-Stream MM Fault Status */
+// replaced by ev5_defs.h #define va 0x206 /* RO - Faulting Virtual Address */
+#define vaForm 0x207 /* RO - Formatted Virtual Address */
+#define mVptBr 0x208 /* WO - Mbox Virtual Page Table Base */
+#define dtbIap 0x209 /* WO - DTB Invalidate All Process */
+#define dtbIa 0x20A /* WO - DTB Invalidate All */
+#define dtbIs 0x20B /* WO - DTB Invalidate Single */
+#define altMode 0x20C /* WO - Alternate Mode */
+// replaced by ev5_defs.h #define cc 0x20D /* WO - Cycle Counter */
+#define ccCtl 0x20E /* WO - Cycle Counter Control */
+// replaced by ev5_defs.h #define mcsr 0x20F /* RW - Mbox Control Register */
+#define dcFlush 0x210 /* WO - Dcache Flush */
+#define dcPerr 0x212 /* RW - Dcache Parity Error Status */
+#define dcTestCtl 0x213 /* RW - Dcache Test Tag Control */
+#define dcTestTag 0x214 /* RW - Dcache Test Tag */
+#define dcTestTagTemp 0x215 /* RW - Dcache Test Tag Temporary */
+#define dcMode 0x216 /* RW - Dcache Mode */
+#define mafMode 0x217 /* RW - Miss Address File Mode */
+
+/*
+**
+** D-Stream MM Fault Status Register (MM_STAT) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ---------------------------------
+** <16:11> 6 OPCODE RO Opcode of faulting instruction
+** <10:06> 5 RA RO Ra field of faulting instruction
+** <5> 1 BAD_VA RO Bad virtual address
+** <4> 1 DTB_MISS RO Reference resulted in DTB miss
+** <3> 1 FOW RO Fault on write
+** <2> 1 FOR RO Fault on read
+** <1> 1 ACV RO Access violation
+** <0> 1 WR RO Reference type
+**
+*/
+
+#define MMSTAT_V_OPC 11
+#define MMSTAT_M_OPC (0x3F<<MMSTAT_V_OPC)
+#define MMSTAT_V_RA 6
+#define MMSTAT_M_RA (0x1F<<MMSTAT_V_RA)
+#define MMSTAT_V_BAD_VA 5
+#define MMSTAT_M_BAD_VA (1<<MMSTAT_V_BAD_VA)
+#define MMSTAT_V_DTB_MISS 4
+#define MMSTAT_M_DTB_MISS (1<<MMSTAT_V_DTB_MISS)
+#define MMSTAT_V_FOW 3
+#define MMSTAT_M_FOW (1<<MMSTAT_V_FOW)
+#define MMSTAT_V_FOR 2
+#define MMSTAT_M_FOR (1<<MMSTAT_V_FOR)
+#define MMSTAT_V_ACV 1
+#define MMSTAT_M_ACV (1<<MMSTAT_V_ACV)
+#define MMSTAT_V_WR 0
+#define MMSTAT_M_WR (1<<MMSTAT_V_WR)
+
+
+/*
+**
+** Mbox Control Register (MCSR) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ---------------------------------
+** <5> 1 DBG1 RW,0 Mbox Debug Packet Select
+** <4> 1 E_BE RW,0 Ebox Big Endian mode enable
+** <3> 1 DBG0 RW,0 Debug Test Select
+** <2:1> 2 SP RW,0 Superpage mode enable
+** <0> 1 M_BE RW,0 Mbox Big Endian mode enable
+**
+*/
+
+#define MCSR_V_DBG1 5
+#define MCSR_M_DBG1 (1<<MCSR_V_DBG1)
+#define MCSR_V_E_BE 4
+#define MCSR_M_E_BE (1<<MCSR_V_E_BE)
+#define MCSR_V_DBG0 3
+#define MCSR_M_DBG0 (1<<MCSR_V_DBG0)
+#define MCSR_V_SP 1
+#define MCSR_M_SP (3<<MCSR_V_SP)
+#define MCSR_V_M_BE 0
+#define MCSR_M_M_BE (1<<MCSR_V_M_BE)
+
+/*
+**
+** Dcache Parity Error Status Register (DCPERR) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ------------------------------------
+** <5> 1 TP1 RO Dcache bank 1 tag parity error
+** <4> 1 TP0 RO Dcache bank 0 tag parity error
+** <3> 1 DP1 RO Dcache bank 1 data parity error
+** <2> 1 DP0 RO Dcache bank 0 data parity error
+** <1> 1 LOCK W1C Locks/clears bits <5:2>
+** <0> 1 SEO W1C Second Dcache parity error occurred
+**
+*/
+
+#define DCPERR_V_TP1 5
+#define DCPERR_M_TP1 (1<<DCPERR_V_TP1)
+#define DCPERR_V_TP0 4
+#define DCPERR_M_TP0 (1<<DCPERR_V_TP0)
+#define DCPERR_V_DP1 3
+#define DCPERR_M_DP1 (1<<DCPERR_V_DP1)
+#define DCPERR_V_DP0 2
+#define DCPERR_M_DP0 (1<<DCPERR_V_DP0)
+#define DCPERR_V_LOCK 1
+#define DCPERR_M_LOCK (1<<DCPERR_V_LOCK)
+#define DCPERR_V_SEO 0
+#define DCPERR_M_SEO (1<<DCPERR_V_SEO)
+
+#define DCPERR_M_ALL (DCPERR_M_LOCK | DCPERR_M_SEO)
+
+/*
+**
+** Dcache Mode Register (DC_MODE) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ---------------------------------
+** <4> 1 DOA RO Hardware Dcache Disable
+** <3> 1 PERR_DIS RW,0 Disable Dcache Parity Error reporting
+** <2> 1 BAD_DP RW,0 Force Dcache data bad parity
+** <1> 1 FHIT RW,0 Force Dcache hit
+** <0> 1 ENA RW,0 Software Dcache Enable
+**
+*/
+
+#define DC_V_DOA 4
+#define DC_M_DOA (1<<DC_V_DOA)
+#define DC_V_PERR_DIS 3
+#define DC_M_PERR_DIS (1<<DC_V_PERR_DIS)
+#define DC_V_BAD_DP 2
+#define DC_M_BAD_DP (1<<DC_V_BAD_DP)
+#define DC_V_FHIT 1
+#define DC_M_FHIT (1<<DC_V_FHIT)
+#define DC_V_ENA 0
+#define DC_M_ENA (1<<DC_V_ENA)
+
+/*
+**
+** Miss Address File Mode Register (MAF_MODE) Bit Summay
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ---------------------------------
+** <7> 1 WB RO,0 If set, pending WB request
+** <6> 1 DREAD RO,0 If set, pending D-read request
+**
+*/
+
+#define MAF_V_WB_PENDING 7
+#define MAF_M_WB_PENDING (1<<MAF_V_WB_PENDING)
+#define MAF_V_DREAD_PENDING 6
+#define MAF_M_DREAD_PENDING (1<<MAF_V_DREAD_PENDING)
+
+/*
+**
+** Cbox IPR Definitions:
+**
+*/
+
+#define scCtl 0x0A8 /* RW - Scache Control */
+#define scStat 0x0E8 /* RO - Scache Error Status */
+#define scAddr 0x188 /* RO - Scache Error Address */
+#define bcCtl 0x128 /* WO - Bcache/System Interface Control */
+#define bcCfg 0x1C8 /* WO - Bcache Configuration Parameters */
+#define bcTagAddr 0x108 /* RO - Bcache Tag */
+#define eiStat 0x168 /* RO - Bcache/System Error Status */
+#define eiAddr 0x148 /* RO - Bcache/System Error Address */
+#define fillSyn 0x068 /* RO - Fill Syndrome */
+#define ldLock 0x1E8 /* RO - LDx_L Address */
+
+/*
+**
+** Scache Control Register (SC_CTL) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ---------------------------------
+** <15:13> 3 SET_EN RW,1 Set enable
+** <12> 1 BLK_SIZE RW,1 Scache/Bcache block size select
+** <11:08> 4 FB_DP RW,0 Force bad data parity
+** <07:02> 6 TAG_STAT RW Tag status and parity
+** <1> 1 FLUSH RW,0 If set, clear all tag valid bits
+** <0> 1 FHIT RW,0 Force hits
+**
+*/
+
+#define SC_V_SET_EN 13
+#define SC_M_SET_EN (7<<SC_V_SET_EN)
+#define SC_V_BLK_SIZE 12
+#define SC_M_BLK_SIZE (1<<SC_V_BLK_SIZE)
+#define SC_V_FB_DP 8
+#define SC_M_FB_DP (0xF<<SC_V_FB_DP)
+#define SC_V_TAG_STAT 2
+#define SC_M_TAG_STAT (0x3F<<SC_V_TAG_STAT)
+#define SC_V_FLUSH 1
+#define SC_M_FLUSH (1<<SC_V_FLUSH)
+#define SC_V_FHIT 0
+#define SC_M_FHIT (1<<SC_V_FHIT)
+
+/*
+**
+** Bcache Control Register (BC_CTL) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ---------------------------------
+** <27> 1 DIS_VIC_BUF WO,0 Disable Scache victim buffer
+** <26> 1 DIS_BAF_BYP WO,0 Disable speculative Bcache reads
+** <25> 1 DBG_MUX_SEL WO,0 Debug MUX select
+** <24:19> 6 PM_MUX_SEL WO,0 Performance counter MUX select
+** <18:17> 2 BC_WAVE WO,0 Number of cycles of wave pipelining
+** <16> 1 TL_PIPE_LATCH WO,0 Pipe system control pins
+** <15> 1 EI_DIS_ERR WO,1 Disable ECC (parity) error
+** <14:13> 2 BC_BAD_DAT WO,0 Force bad data
+** <12:08> 5 BC_TAG_STAT WO Bcache tag status and parity
+** <7> 1 BC_FHIT WO,0 Bcache force hit
+** <6> 1 EI_ECC WO,1 ECC or byte parity mode
+** <5> 1 VTM_FIRST WO,1 Drive out victim block address first
+** <4> 1 CORR_FILL_DAT WO,1 Correct fill data
+** <3> 1 EI_CMD_GRP3 WO,0 Drive MB command to external pins
+** <2> 1 EI_CMD_GRP2 WO,0 Drive LOCK & SET_DIRTY to ext. pins
+** <1> 1 ALLOC_CYC WO,0 Allocate cycle for non-cached LDs.
+** <0> 1 BC_ENA W0,0 Bcache enable
+**
+*/
+#define BC_V_DIS_SC_VIC_BUF 27
+#define BC_M_DIS_SC_VIC_BUF (1<<BC_V_DIS_SC_VIC_BUF)
+#define BC_V_DIS_BAF_BYP 26
+#define BC_M_DIS_BAF_BYP (1<<BC_V_DIS_BAF_BYP)
+#define BC_V_DBG_MUX_SEL 25
+#define BC_M_DBG_MUX_SEL (1<<BC_V_DBG_MUX_SEL)
+#define BC_V_PM_MUX_SEL 19
+#define BC_M_PM_MUX_SEL (0x3F<<BC_V_PM_MUX_SEL)
+#define BC_V_BC_WAVE 17
+#define BC_M_BC_WAVE (3<<BC_V_BC_WAVE)
+#define BC_V_TL_PIPE_LATCH 16
+#define BC_M_TL_PIPE_LATCH (1<<BC_V_TL_PIPE_LATCH)
+#define BC_V_EI_DIS_ERR 15
+#define BC_M_EI_DIS_ERR (1<<BC_V_EI_DIS_ERR)
+#define BC_V_BC_BAD_DAT 13
+#define BC_M_BC_BAD_DAT (3<<BC_V_BC_BAD_DAT)
+#define BC_V_BC_TAG_STAT 8
+#define BC_M_BC_TAG_STAT (0x1F<<BC_V_BC_TAG_STAT)
+#define BC_V_BC_FHIT 7
+#define BC_M_BC_FHIT (1<<BC_V_BC_FHIT)
+#define BC_V_EI_ECC_OR_PARITY 6
+#define BC_M_EI_ECC_OR_PARITY (1<<BC_V_EI_ECC_OR_PARITY)
+#define BC_V_VTM_FIRST 5
+#define BC_M_VTM_FIRST (1<<BC_V_VTM_FIRST)
+#define BC_V_CORR_FILL_DAT 4
+#define BC_M_CORR_FILL_DAT (1<<BC_V_CORR_FILL_DAT)
+#define BC_V_EI_CMD_GRP3 3
+#define BC_M_EI_CMD_GRP3 (1<<BC_V_EI_CMD_GRP3)
+#define BC_V_EI_CMD_GRP2 2
+#define BC_M_EI_CMD_GRP2 (1<<BC_V_EI_CMD_GRP2)
+#define BC_V_ALLOC_CYC 1
+#define BC_M_ALLOC_CYC (1<<BC_V_ALLOC_CYC)
+#define BC_V_BC_ENA 0
+#define BC_M_BC_ENA (1<<BC_V_BC_ENA)
+
+#define BC_K_DFAULT \
+ (((BC_M_EI_DIS_ERR) | \
+ (BC_M_EI_ECC_OR_PARITY) | \
+ (BC_M_VTM_FIRST) | \
+ (BC_M_CORR_FILL_DAT))>>1)
+/*
+**
+** Bcache Configuration Register (BC_CONFIG) Bit Summary
+**
+** Extent Size Name Type Function
+** ------ ---- ---- ---- ---------------------------------
+** <35:29> 7 RSVD WO Reserved - Must Be Zero
+** <28:20> 9 WE_CTL WO,0 Bcache write enable control
+** <19:19> 1 RSVD WO,0 Reserved - Must Be Zero
+** <18:16> 3 WE_OFF WO,1 Bcache fill write enable pulse offset
+** <15:15> 1 RSVD WO,0 Reserved - Must Be Zero
+** <14:12> 3 RD_WR_SPC WO,7 Bcache private read/write spacing
+** <11:08> 4 WR_SPD WO,4 Bcache write speed in CPU cycles
+** <07:04> 4 RD_SPD WO,4 Bcache read speed in CPU cycles
+** <03:03> 1 RSVD WO,0 Reserved - Must Be Zero
+** <02:00> 3 SIZE WO,1 Bcache size
+*/
+#define BC_V_WE_CTL 20
+#define BC_M_WE_CTL (0x1FF<<BC_V_WE_CTL)
+#define BC_V_WE_OFF 16
+#define BC_M_WE_OFF (0x7<<BC_V_WE_OFF)
+#define BC_V_RD_WR_SPC 12
+#define BC_M_RD_WR_SPC (0x7<<BC_V_RD_WR_SPC)
+#define BC_V_WR_SPD 8
+#define BC_M_WR_SPD (0xF<<BC_V_WR_SPD)
+#define BC_V_RD_SPD 4
+#define BC_M_RD_SPD (0xF<<BC_V_RD_SPD)
+#define BC_V_SIZE 0
+#define BC_M_SIZE (0x7<<BC_V_SIZE)
+
+#define BC_K_CONFIG \
+ ((0x1<<BC_V_WE_OFF) | \
+ (0x7<<BC_V_RD_WR_SPC) | \
+ (0x4<<BC_V_WR_SPD) | \
+ (0x4<<BC_V_RD_SPD) | \
+ (0x1<<BC_V_SIZE))
+
+/*
+**
+** DECchip 21164 Privileged Architecture Library Entry Offsets:
+**
+** Entry Name Offset (Hex)
+**
+** RESET 0000
+** IACCVIO 0080
+** INTERRUPT 0100
+** ITB_MISS 0180
+** DTB_MISS (Single) 0200
+** DTB_MISS (Double) 0280
+** UNALIGN 0300
+** D_FAULT 0380
+** MCHK 0400
+** OPCDEC 0480
+** ARITH 0500
+** FEN 0580
+** CALL_PAL (Privileged) 2000
+** CALL_PAL (Unprivileged) 3000
+**
+*/
+
+#define PAL_RESET_ENTRY 0x0000
+#define PAL_IACCVIO_ENTRY 0x0080
+#define PAL_INTERRUPT_ENTRY 0x0100
+#define PAL_ITB_MISS_ENTRY 0x0180
+#define PAL_DTB_MISS_ENTRY 0x0200
+#define PAL_DOUBLE_MISS_ENTRY 0x0280
+#define PAL_UNALIGN_ENTRY 0x0300
+#define PAL_D_FAULT_ENTRY 0x0380
+#define PAL_MCHK_ENTRY 0x0400
+#define PAL_OPCDEC_ENTRY 0x0480
+#define PAL_ARITH_ENTRY 0x0500
+#define PAL_FEN_ENTRY 0x0580
+#define PAL_CALL_PAL_PRIV_ENTRY 0x2000
+#define PAL_CALL_PAL_UNPRIV_ENTRY 0x3000
+
+/*
+**
+** Architecturally Reserved Opcode (PALRES) Definitions:
+**
+*/
+
+#define mtpr hw_mtpr
+#define mfpr hw_mfpr
+
+#define ldl_a hw_ldl/a
+#define ldq_a hw_ldq/a
+#define stq_a hw_stq/a
+#define stl_a hw_stl/a
+
+#define ldl_p hw_ldl/p
+#define ldq_p hw_ldq/p
+#define stl_p hw_stl/p
+#define stq_p hw_stq/p
+
+/*
+** Virtual PTE fetch variants of HW_LD.
+*/
+#define ld_vpte hw_ldq/v
+
+/*
+** Physical mode load-lock and store-conditional variants of
+** HW_LD and HW_ST.
+*/
+
+#define ldq_lp hw_ldq/pl
+#define stq_cp hw_stq/pc
+
+/*
+**
+** General Purpose Register Definitions:
+**
+*/
+
+#define r0 $0
+#define r1 $1
+#define r2 $2
+#define r3 $3
+#define r4 $4
+#define r5 $5
+#define r6 $6
+#define r7 $7
+#define r8 $8
+#define r9 $9
+#define r10 $10
+#define r11 $11
+#define r12 $12
+#define r13 $13
+#define r14 $14
+#define r15 $15
+#define r16 $16
+#define r17 $17
+#define r18 $18
+#define r19 $19
+#define r20 $20
+#define r21 $21
+#define r22 $22
+#define r23 $23
+#define r24 $24
+#define r25 $25
+#define r26 $26
+#define r27 $27
+#define r28 $28
+#define r29 $29
+#define r30 $30
+#define r31 $31
+
+/*
+**
+** Floating Point Register Definitions:
+**
+*/
+
+#define f0 $f0
+#define f1 $f1
+#define f2 $f2
+#define f3 $f3
+#define f4 $f4
+#define f5 $f5
+#define f6 $f6
+#define f7 $f7
+#define f8 $f8
+#define f9 $f9
+#define f10 $f10
+#define f11 $f11
+#define f12 $f12
+#define f13 $f13
+#define f14 $f14
+#define f15 $f15
+#define f16 $f16
+#define f17 $f17
+#define f18 $f18
+#define f19 $f19
+#define f20 $f20
+#define f21 $f21
+#define f22 $f22
+#define f23 $f23
+#define f24 $f24
+#define f25 $f25
+#define f26 $f26
+#define f27 $f27
+#define f28 $f28
+#define f29 $f29
+#define f30 $f30
+#define f31 $f31
+
+/*
+**
+** PAL Temporary Register Definitions:
+**
+*/
+
+// covered by fetch distribution..pb Nov/95
+
+// #define pt0 0x140
+// #define pt1 0x141
+// #define pt2 0x142
+// #define pt3 0x143
+// #define pt4 0x144
+// #define pt5 0x145
+// #define pt6 0x146
+// #define pt7 0x147
+// #define pt8 0x148
+// #define pt9 0x149
+// #define pt10 0x14A
+// #define pt11 0x14B
+// #define pt12 0x14C
+// #define pt13 0x14D
+// #define pt14 0x14E
+// #define pt15 0x14F
+// #define pt16 0x150
+// #define pt17 0x151
+// #define pt18 0x152
+// #define pt19 0x153
+// #define pt20 0x154
+// #define pt21 0x155
+// #define pt22 0x156
+// #define pt23 0x157
+
+/*
+** PAL Shadow Registers:
+**
+** The DECchip 21164 shadows r8-r14 and r25 when in PALmode and
+** ICSR<SDE> = 1.
+*/
+
+#define p0 r8 /* ITB/DTB Miss Scratch */
+#define p1 r9 /* ITB/DTB Miss Scratch */
+#define p2 r10 /* ITB/DTB Miss Scratch */
+#define p3 r11
+// #define ps r11 /* Processor Status */
+#define p4 r12 /* Local Scratch */
+#define p5 r13 /* Local Scratch */
+#define p6 r14 /* Local Scratch */
+#define p7 r25 /* Local Scratch */
+
+/*
+** SRM Defined State Definitions:
+*/
+
+/*
+** This table is an accounting of the DECchip 21164 storage used to
+** implement the SRM defined state for OSF/1.
+**
+** IPR Name Internal Storage
+** -------- ----------------
+** Processor Status ps, dtbCm, ipl, r11
+** Program Counter Ibox
+** Interrupt Entry ptEntInt
+** Arith Trap Entry ptEntArith
+** MM Fault Entry ptEntMM
+** Unaligned Access Entry ptEntUna
+** Instruction Fault Entry ptEntIF
+** Call System Entry ptEntSys
+** User Stack Pointer ptUsp
+** Kernel Stack Pointer ptKsp
+** Kernel Global Pointer ptKgp
+** System Value ptSysVal
+** Page Table Base Register ptPtbr
+** Virtual Page Table Base iVptBr, mVptBr
+** Process Control Block Base ptPcbb
+** Address Space Number itbAsn, dtbAsn
+** Cycle Counter cc, ccCtl
+** Float Point Enable icsr
+** Lock Flag Cbox/System
+** Unique PCB
+** Who-Am-I ptWhami
+*/
+
+#define ptEntUna pt2 /* Unaligned Access Dispatch Entry */
+#define ptImpure pt3 /* Pointer To PAL Scratch Area */
+#define ptEntIF pt7 /* Instruction Fault Dispatch Entry */
+#define ptIntMask pt8 /* Interrupt Enable Mask */
+#define ptEntSys pt9 /* Call System Dispatch Entry */
+#define ptTrap pt11
+#define ptEntInt pt11 /* Hardware Interrupt Dispatch Entry */
+#define ptEntArith pt12 /* Arithmetic Trap Dispatch Entry */
+#if defined(KDEBUG)
+#define ptEntDbg pt13 /* Kernel Debugger Dispatch Entry */
+#endif /* KDEBUG */
+#define ptMisc pt16 /* Miscellaneous Flags */
+#define ptWhami pt16 /* Who-Am-I Register Pt16<15:8> */
+#define ptMces pt16 /* Machine Check Error Summary Pt16<4:0> */
+#define ptSysVal pt17 /* Per-Processor System Value */
+#define ptUsp pt18 /* User Stack Pointer */
+#define ptKsp pt19 /* Kernel Stack Pointer */
+#define ptPtbr pt20 /* Page Table Base Register */
+#define ptEntMM pt21 /* MM Fault Dispatch Entry */
+#define ptKgp pt22 /* Kernel Global Pointer */
+#define ptPcbb pt23 /* Process Control Block Base */
+
+/*
+**
+** Miscellaneous PAL State Flags (ptMisc) Bit Summary
+**
+** Extent Size Name Function
+** ------ ---- ---- ---------------------------------
+** <55:48> 8 SWAP Swap PALcode flag -- character 'S'
+** <47:32> 16 MCHK Machine Check Error code
+** <31:16> 16 SCB System Control Block vector
+** <15:08> 8 WHAMI Who-Am-I identifier
+** <04:00> 5 MCES Machine Check Error Summary bits
+**
+*/
+
+#define PT16_V_MCES 0
+#define PT16_V_WHAMI 8
+#define PT16_V_SCB 16
+#define PT16_V_MCHK 32
+#define PT16_V_SWAP 48
+
+#endif /* DC21164FROMGASSOURCES_INCLUDED */
diff --git a/system/alpha/h/ev5_alpha_defs.h b/system/alpha/h/ev5_alpha_defs.h
new file mode 100644
index 000000000..d0264a4ca
--- /dev/null
+++ b/system/alpha/h/ev5_alpha_defs.h
@@ -0,0 +1,314 @@
+/*
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef EV5_ALPHA_DEFS_INCLUDED
+#define EV5_ALPHA_DEFS_INCLUDED 1
+
+// from ev5_alpha_defs.mar from Lance's fetch directory
+// Lower-caseified and $ signs removed ... pb Nov/95
+
+//
+// PS Layout - PS
+// Loc Size name function
+// ------ ------ ______ -----------------------------------
+// <31:29> 3 SA stack alignment
+// <31:13> 24 RES Reserved MBZ
+// <12:8> 5 IPL Priority level
+// <7> 1 VMM Virtual Mach Monitor
+// <6:5> 2 RES Reserved MBZ
+// <4:3> 2 CM Current Mode
+// <2> 1 IP Interrupt Pending
+// <1:0> 2 SW Software bits
+//
+
+#define ps_v_sw 0
+#define ps_m_sw (3<<ps_v_sw)
+
+#define ps_v_ip 2
+#define ps_m_ip (1<<ps_v_ip)
+
+#define ps_v_cm 3
+#define ps_m_cm (3<<ps_v_cm)
+
+#define ps_v_vmm 7
+#define ps_m_vmm (1<<ps_v_vmm)
+
+#define ps_v_ipl 8
+#define ps_m_ipl (0x1f<<ps_v_ipl)
+
+#define ps_v_sp (0x38)
+#define ps_m_sp (0x3f<<ps_v_sp)
+
+
+#define ps_c_kern (0x00)
+#define ps_c_exec (0x08)
+#define ps_c_supr (0x10)
+#define ps_c_user (0x18)
+#define ps_c_ipl0 (0x0000)
+#define ps_c_ipl1 (0x0100)
+#define ps_c_ipl2 (0x0200)
+#define ps_c_ipl3 (0x0300)
+#define ps_c_ipl4 (0x0400)
+#define ps_c_ipl5 (0x0500)
+#define ps_c_ipl6 (0x0600)
+#define ps_c_ipl7 (0x0700)
+#define ps_c_ipl8 (0x0800)
+#define ps_c_ipl9 (0x0900)
+#define ps_c_ipl10 (0x0A00)
+#define ps_c_ipl11 (0x0B00)
+#define ps_c_ipl12 (0x0C00)
+#define ps_c_ipl13 (0x0D00)
+#define ps_c_ipl14 (0x0E00)
+#define ps_c_ipl15 (0x0F00)
+#define ps_c_ipl16 (0x1000)
+#define ps_c_ipl17 (0x1100)
+#define ps_c_ipl18 (0x1200)
+#define ps_c_ipl19 (0x1300)
+#define ps_c_ipl20 (0x1400)
+#define ps_c_ipl21 (0x1500)
+#define ps_c_ipl22 (0x1600)
+#define ps_c_ipl23 (0x1700)
+#define ps_c_ipl24 (0x1800)
+#define ps_c_ipl25 (0x1900)
+#define ps_c_ipl26 (0x1A00)
+#define ps_c_ipl27 (0x1B00)
+#define ps_c_ipl28 (0x1C00)
+#define ps_c_ipl29 (0x1D00)
+#define ps_c_ipl30 (0x1E00)
+#define ps_c_ipl31 (0x1F00)
+
+//
+// PTE layout - symbol prefix PTE_
+//
+// Loc Size name function
+// ------ ------ ------ -----------------------------------
+// <63:32> 32 PFN Page Frame Number
+// <31:16> 16 SOFT Bits reserved for software use
+// <15> 1 UWE User write enable
+// <14> 1 SWE Super write enable
+// <13> 1 EWE Exec write enable
+// <12> 1 KWE Kernel write enable
+// <11> 1 URE User read enable
+// <10> 1 SRE Super read enable
+// <9> 1 ERE Exec read enable
+// <8> 1 KRE Kernel read enable
+// <7:6> 2 RES Reserved SBZ
+// <5> 1 HPF Huge Page Flag
+// <4> 1 ASM Wild card address space number match
+// <3> 1 FOE Fault On execute
+// <2> 1 FOW Fault On Write
+// <1> 1 FOR Fault On Read
+// <0> 1 V valid bit
+//
+
+#define pte_v_pfn 32
+#define pte_m_soft (0xFFFF0000)
+#define pte_v_soft 16
+#define pte_m_uwe (0x8000)
+#define pte_v_uwe 15
+#define pte_m_swe (0x4000)
+#define pte_v_swe 14
+#define pte_m_ewe (0x2000)
+#define pte_v_ewe 13
+#define pte_m_kwe (0x1000)
+#define pte_v_kwe 12
+#define pte_m_ure (0x0800)
+#define pte_v_ure 11
+#define pte_m_sre (0x0400)
+#define pte_v_sre 10
+#define pte_m_ere (0x0200)
+#define pte_v_ere 9
+#define pte_m_kre (0x0100)
+#define pte_v_kre 8
+#define pte_m_hpf (0x0020)
+#define pte_v_hpf 5
+#define pte_m_asm (0x0010)
+#define pte_v_asm 4
+#define pte_m_foe (0x0008)
+#define pte_v_foe 3
+#define pte_m_fow (0x0004)
+#define pte_v_fow 2
+#define pte_m_for (0x0002)
+#define pte_v_for 1
+#define pte_m_v (0x0001)
+#define pte_v_v 0
+
+//
+// VA layout - symbol prefix VA_
+//
+// Loc Size name function
+// ------ ------ ------- -----------------------------------
+// <42:33> 10 SEG1 First seg table offset for mapping
+// <32:23> 10 SEG2 Second seg table offset for mapping
+// <22:13> 10 SEG3 Third seg table offset for mapping
+// <12:0> 13 OFFSET Byte within page
+//
+
+#define va_m_offset (0x000000001FFF)
+#define va_v_offset 0
+#define va_m_seg3 (0x0000007FE000)
+#define va_v_seg3 13
+#define va_m_seg2 (0x0001FF800000)
+#define va_v_seg2 23
+#define va_m_seg1 (0x7FE00000000)
+#define va_v_seg1 33
+
+//
+//PRIVILEGED CONTEXT BLOCK (PCB)
+//
+#define pcb_q_ksp 0
+#define pcb_q_esp 8
+#define pcb_q_ssp 16
+#define pcb_q_usp 24
+#define pcb_q_ptbr 32
+#define pcb_q_asn 40
+#define pcb_q_ast 48
+#define pcb_q_fen 56
+#define pcb_q_cc 64
+#define pcb_q_unq 72
+#define pcb_q_sct 80
+
+#define pcb_v_asten 0
+#define pcb_m_asten (0x0f<<pcb_v_asten)
+#define pcb_v_astsr 4
+#define pcb_m_astsr (0x0f<<pcb_v_astsr)
+#define pcb_v_dat 63
+#define pcb_v_pme 62
+
+//
+// SYSTEM CONTROL BLOCK (SCB)
+//
+
+#define scb_v_fen (0x0010)
+#define scb_v_acv (0x0080)
+#define scb_v_tnv (0x0090)
+#define scb_v_for (0x00A0)
+#define scb_v_fow (0x00B0)
+#define scb_v_foe (0x00C0)
+#define scb_v_arith (0x0200)
+#define scb_v_kast (0x0240)
+#define scb_v_east (0x0250)
+#define scb_v_sast (0x0260)
+#define scb_v_uast (0x0270)
+#define scb_v_unalign (0x0280)
+#define scb_v_bpt (0x0400)
+#define scb_v_bugchk (0x0410)
+#define scb_v_opcdec (0x0420)
+#define scb_v_illpal (0x0430)
+#define scb_v_trap (0x0440)
+#define scb_v_chmk (0x0480)
+#define scb_v_chme (0x0490)
+#define scb_v_chms (0x04A0)
+#define scb_v_chmu (0x04B0)
+#define scb_v_sw0 (0x0500)
+#define scb_v_sw1 (0x0510)
+#define scb_v_sw2 (0x0520)
+#define scb_v_sw3 (0x0530)
+#define scb_v_sw4 (0x0540)
+#define scb_v_sw5 (0x0550)
+#define scb_v_sw6 (0x0560)
+#define scb_v_sw7 (0x0570)
+#define scb_v_sw8 (0x0580)
+#define scb_v_sw9 (0x0590)
+#define scb_v_sw10 (0x05A0)
+#define scb_v_sw11 (0x05B0)
+#define scb_v_sw12 (0x05C0)
+#define scb_v_sw13 (0x05D0)
+#define scb_v_sw14 (0x05E0)
+#define scb_v_sw15 (0x05F0)
+#define scb_v_clock (0x0600)
+#define scb_v_inter (0x0610)
+#define scb_v_sys_corr_err (0x0620)
+#define scb_v_proc_corr_err (0x0630)
+#define scb_v_pwrfail (0x0640)
+#define scb_v_perfmon (0x0650)
+#define scb_v_sysmchk (0x0660)
+#define scb_v_procmchk (0x0670)
+#define scb_v_passive_rel (0x06F0)
+
+//
+// Stack frame (FRM)
+//
+
+#define frm_v_r2 (0x0000)
+#define frm_v_r3 (0x0008)
+#define frm_v_r4 (0x0010)
+#define frm_v_r5 (0x0018)
+#define frm_v_r6 (0x0020)
+#define frm_v_r7 (0x0028)
+#define frm_v_pc (0x0030)
+#define frm_v_ps (0x0038)
+
+//
+// Exeception summary register (EXS)
+//
+// exs_v_swc <0> ; Software completion
+// exs_v_inv <1> ; Ivalid operation
+// exs_v_dze <2> ; Div by zero
+// exs_v_fov <3> ; Floating point overflow
+// exs_v_unf <4> ; Floating point underflow
+// exs_v_ine <5> ; Floating point inexact
+// exs_v_iov <6> ; Floating convert to integer overflow
+#define exs_v_swc 0
+#define exs_v_inv 1
+#define exs_v_dze 2
+#define exs_v_fov 3
+#define exs_v_unf 4
+#define exs_v_ine 5
+#define exs_v_iov 6
+
+#define exs_m_swc (1<<exs_v_swc)
+#define exs_m_inv (1<<exs_v_inv)
+#define exs_m_dze (1<<exs_v_dze)
+#define exs_m_fov (1<<exs_v_fov)
+#define exs_m_unf (1<<exs_v_unf)
+#define exs_m_ine (1<<exs_v_ine)
+#define exs_m_iov (1<<exs_v_iov)
+
+//
+// machine check error summary register (mces)
+//
+// mces_v_mchk <0> ; machine check in progress
+// mces_v_sce <1> ; system correctable error
+// mces_v_pce <2> ; processor correctable error
+// mces_v_dpc <3> ; disable reporting of processor correctable errors
+// mces_v_dsc <4> ; disable reporting of system correctable errors
+#define mces_v_mchk 0
+#define mces_v_sce 1
+#define mces_v_pce 2
+#define mces_v_dpc 3
+#define mces_v_dsc 4
+
+#define mces_m_mchk (1<<mces_v_mchk)
+#define mces_m_sce (1<<mces_v_sce)
+#define mces_m_pce (1<<mces_v_pce)
+#define mces_m_dpc (1<<mces_v_dpc)
+#define mces_m_dsc (1<<mces_v_dsc)
+#define mces_m_all ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce) | (1<<mces_v_dpc) | (1<<mces_v_dsc))
+
+#endif
diff --git a/system/alpha/h/ev5_defs.h b/system/alpha/h/ev5_defs.h
new file mode 100644
index 000000000..c8b2f5b2e
--- /dev/null
+++ b/system/alpha/h/ev5_defs.h
@@ -0,0 +1,598 @@
+/*
+ * Copyright (c) 1995 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef EV5_DEFS_INCLUDED
+#define EV5_DEFS_INCLUDED 1
+
+// adapted from the version emailed to lance..pb Nov/95
+
+// In the definitions below, registers are annotated with one of the
+// following symbols:
+//
+// RW - The register may be read and written
+// RO - The register may only be read
+// WO - The register may only be written
+//
+// For RO and WO registers, all bits and fields within the register
+// are also read-only or write-only. For RW registers, each bit or
+// field within the register is annotated with one of the following:
+//
+// RW - The bit/field may be read and written
+// RO - The bit/field may be read; writes are ignored
+// WO - The bit/field may be written; reads return an UNPREDICTABLE result
+// WZ - The bit/field may be written; reads return a 0
+// WC - The bit/field may be read; writes cause state to clear
+// RC - The bit/field may be read, which also causes state to clear;
+// writes are ignored
+// Architecturally-defined (SRM) registers for EVMS
+
+#define pt0 320
+#define pt1 321
+#define pt2 322
+#define pt3 323
+#define pt4 324
+#define pt5 325
+#define pt6 326
+#define pt7 327
+#define pt8 328
+#define pt9 329
+#define pt10 330
+#define pt11 331
+#define pt12 332
+#define pt13 333
+#define pt14 334
+#define pt15 335
+#define pt16 336
+#define pt17 337
+#define pt18 338
+#define pt19 339
+#define pt20 340
+#define pt21 341
+#define pt22 342
+#define pt23 343
+#define cbox_ipr_offset 16777200
+#define sc_ctl 168
+#define sc_stat 232
+#define sc_addr 392
+#define sc_addr_nm 392
+#define sc_addr_fhm 392
+#define bc_ctl 296
+#define bc_config 456
+#define ei_stat 360
+#define ei_addr 328
+#define fill_syn 104
+#define bc_tag_addr 264
+#define ld_lock 488
+#define aster 266
+#define astrr 265
+#define exc_addr 267
+#define exc_sum 268
+#define exc_mask 269
+#define hwint_clr 277
+#define ic_flush_ctl 281
+#define icperr_stat 282
+#define ic_perr_stat 282
+#define ic_row_map 283
+#define icsr 280
+#define ifault_va_form 274
+#define intid 273
+#define ipl 272
+#define isr 256
+#define itb_is 263
+#define itb_asn 259
+#define itb_ia 261
+#define itb_iap 262
+#define itb_pte 258
+#define itb_pte_temp 260
+#define itb_tag 257
+#define ivptbr 275
+#define pal_base 270
+#define pmctr 284
+// this is not the register ps .. pb #define ps 271
+#define sirr 264
+#define sl_txmit 278
+#define sl_rcv 279
+#define alt_mode 524
+#define cc 525
+#define cc_ctl 526
+#define dc_flush 528
+#define dcperr_stat 530
+#define dc_test_ctl 531
+#define dc_test_tag 532
+#define dc_test_tag_temp 533
+#define dtb_asn 512
+#define dtb_cm 513
+#define dtb_ia 522
+#define dtb_iap 521
+#define dtb_is 523
+#define dtb_pte 515
+#define dtb_pte_temp 516
+#define dtb_tag 514
+#define mcsr 527
+#define dc_mode 534
+#define maf_mode 535
+#define mm_stat 517
+#define mvptbr 520
+#define va 518
+#define va_form 519
+#define ev5_srm__ps 0
+#define ev5_srm__pc 0
+#define ev5_srm__asten 0
+#define ev5_srm__astsr 0
+#define ev5_srm__ipir 0
+#define ev5_srm__ipl 0
+#define ev5_srm__mces 0
+#define ev5_srm__pcbb 0
+#define ev5_srm__prbr 0
+#define ev5_srm__ptbr 0
+#define ev5_srm__scbb 0
+#define ev5_srm__sirr 0
+#define ev5_srm__sisr 0
+#define ev5_srm__tbchk 0
+#define ev5_srm__tb1a 0
+#define ev5_srm__tb1ap 0
+#define ev5_srm__tb1ad 0
+#define ev5_srm__tb1ai 0
+#define ev5_srm__tbis 0
+#define ev5_srm__ksp 0
+#define ev5_srm__esp 0
+#define ev5_srm__ssp 0
+#define ev5_srm__usp 0
+#define ev5_srm__vptb 0
+#define ev5_srm__whami 0
+#define ev5_srm__cc 0
+#define ev5_srm__unq 0
+// processor-specific iprs.
+#define ev5__sc_ctl 168
+#define ev5__sc_stat 232
+#define ev5__sc_addr 392
+#define ev5__bc_ctl 296
+#define ev5__bc_config 456
+#define bc_config_k_size_1mb 1
+#define bc_config_k_size_2mb 2
+#define bc_config_k_size_4mb 3
+#define bc_config_k_size_8mb 4
+#define bc_config_k_size_16mb 5
+#define bc_config_k_size_32mb 6
+#define bc_config_k_size_64mb 7
+#define ev5__ei_stat 360
+#define ev5__ei_addr 328
+#define ev5__fill_syn 104
+#define ev5__bc_tag_addr 264
+#define ev5__aster 266
+#define ev5__astrr 265
+#define ev5__exc_addr 267
+#define exc_addr_v_pa 2
+#define exc_addr_s_pa 62
+#define ev5__exc_sum 268
+#define ev5__exc_mask 269
+#define ev5__hwint_clr 277
+#define ev5__ic_flush_ctl 281
+#define ev5__icperr_stat 282
+#define ev5__ic_perr_stat 282
+#define ev5__ic_row_map 283
+#define ev5__icsr 280
+#define ev5__ifault_va_form 274
+#define ev5__ifault_va_form_nt 274
+#define ifault_va_form_nt_v_vptb 30
+#define ifault_va_form_nt_s_vptb 34
+#define ev5__intid 273
+#define ev5__ipl 272
+#define ev5__itb_is 263
+#define ev5__itb_asn 259
+#define ev5__itb_ia 261
+#define ev5__itb_iap 262
+#define ev5__itb_pte 258
+#define ev5__itb_pte_temp 260
+#define ev5__itb_tag 257
+#define ev5__ivptbr 275
+#define ivptbr_v_vptb 30
+#define ivptbr_s_vptb 34
+#define ev5__pal_base 270
+#define ev5__pmctr 284
+#define ev5__ps 271
+#define ev5__isr 256
+#define ev5__sirr 264
+#define ev5__sl_txmit 278
+#define ev5__sl_rcv 279
+#define ev5__alt_mode 524
+#define ev5__cc 525
+#define ev5__cc_ctl 526
+#define ev5__dc_flush 528
+#define ev5__dcperr_stat 530
+#define ev5__dc_test_ctl 531
+#define ev5__dc_test_tag 532
+#define ev5__dc_test_tag_temp 533
+#define ev5__dtb_asn 512
+#define ev5__dtb_cm 513
+#define ev5__dtb_ia 522
+#define ev5__dtb_iap 521
+#define ev5__dtb_is 523
+#define ev5__dtb_pte 515
+#define ev5__dtb_pte_temp 516
+#define ev5__dtb_tag 514
+#define ev5__mcsr 527
+#define ev5__dc_mode 534
+#define ev5__maf_mode 535
+#define ev5__mm_stat 517
+#define ev5__mvptbr 520
+#define ev5__va 518
+#define ev5__va_form 519
+#define ev5__va_form_nt 519
+#define va_form_nt_s_va 19
+#define va_form_nt_v_vptb 30
+#define va_form_nt_s_vptb 34
+#define ev5s_ev5_def 10
+#define ev5_def 0
+// cbox registers.
+#define sc_ctl_v_sc_fhit 0
+#define sc_ctl_v_sc_flush 1
+#define sc_ctl_s_sc_tag_stat 6
+#define sc_ctl_v_sc_tag_stat 2
+#define sc_ctl_s_sc_fb_dp 4
+#define sc_ctl_v_sc_fb_dp 8
+#define sc_ctl_v_sc_blk_size 12
+#define sc_ctl_s_sc_set_en 3
+#define sc_ctl_v_sc_set_en 13
+#define sc_ctl_s_sc_soft_repair 3
+#define sc_ctl_v_sc_soft_repair 16
+#define sc_stat_s_sc_tperr 3
+#define sc_stat_v_sc_tperr 0
+#define sc_stat_s_sc_dperr 8
+#define sc_stat_v_sc_dperr 3
+#define sc_stat_s_cbox_cmd 5
+#define sc_stat_v_cbox_cmd 11
+#define sc_stat_v_sc_scnd_err 16
+#define sc_addr_fhm_v_sc_tag_parity 4
+#define sc_addr_fhm_s_tag_stat_sb0 3
+#define sc_addr_fhm_v_tag_stat_sb0 5
+#define sc_addr_fhm_s_tag_stat_sb1 3
+#define sc_addr_fhm_v_tag_stat_sb1 8
+#define sc_addr_fhm_s_ow_mod0 2
+#define sc_addr_fhm_v_ow_mod0 11
+#define sc_addr_fhm_s_ow_mod1 2
+#define sc_addr_fhm_v_ow_mod1 13
+#define sc_addr_fhm_s_tag_lo 17
+#define sc_addr_fhm_v_tag_lo 15
+#define sc_addr_fhm_s_tag_hi 7
+#define sc_addr_fhm_v_tag_hi 32
+#define bc_ctl_v_bc_enabled 0
+#define bc_ctl_v_alloc_cyc 1
+#define bc_ctl_v_ei_opt_cmd 2
+#define bc_ctl_v_ei_opt_cmd_mb 3
+#define bc_ctl_v_corr_fill_dat 4
+#define bc_ctl_v_vtm_first 5
+#define bc_ctl_v_ei_ecc_or_parity 6
+#define bc_ctl_v_bc_fhit 7
+#define bc_ctl_s_bc_tag_stat 5
+#define bc_ctl_v_bc_tag_stat 8
+#define bc_ctl_s_bc_bad_dat 2
+#define bc_ctl_v_bc_bad_dat 13
+#define bc_ctl_v_ei_dis_err 15
+#define bc_ctl_v_tl_pipe_latch 16
+#define bc_ctl_s_bc_wave_pipe 2
+#define bc_ctl_v_bc_wave_pipe 17
+#define bc_ctl_s_pm_mux_sel 6
+#define bc_ctl_v_pm_mux_sel 19
+#define bc_ctl_v_dbg_mux_sel 25
+#define bc_ctl_v_dis_baf_byp 26
+#define bc_ctl_v_dis_sc_vic_buf 27
+#define bc_ctl_v_dis_sys_addr_par 28
+#define bc_ctl_v_read_dirty_cln_shr 29
+#define bc_ctl_v_write_read_bubble 30
+#define bc_ctl_v_bc_wave_pipe_2 31
+#define bc_ctl_v_auto_dack 32
+#define bc_ctl_v_dis_byte_word 33
+#define bc_ctl_v_stclk_delay 34
+#define bc_ctl_v_write_under_miss 35
+#define bc_config_s_bc_size 3
+#define bc_config_v_bc_size 0
+#define bc_config_s_bc_rd_spd 4
+#define bc_config_v_bc_rd_spd 4
+#define bc_config_s_bc_wr_spd 4
+#define bc_config_v_bc_wr_spd 8
+#define bc_config_s_bc_rd_wr_spc 3
+#define bc_config_v_bc_rd_wr_spc 12
+#define bc_config_s_fill_we_offset 3
+#define bc_config_v_fill_we_offset 16
+#define bc_config_s_bc_we_ctl 9
+#define bc_config_v_bc_we_ctl 20
+// cbox registers, continued
+#define ei_stat_s_sys_id 4
+#define ei_stat_v_sys_id 24
+#define ei_stat_v_bc_tperr 28
+#define ei_stat_v_bc_tc_perr 29
+#define ei_stat_v_ei_es 30
+#define ei_stat_v_cor_ecc_err 31
+#define ei_stat_v_unc_ecc_err 32
+#define ei_stat_v_ei_par_err 33
+#define ei_stat_v_fil_ird 34
+#define ei_stat_v_seo_hrd_err 35
+//
+#define bc_tag_addr_v_hit 12
+#define bc_tag_addr_v_tagctl_p 13
+#define bc_tag_addr_v_tagctl_d 14
+#define bc_tag_addr_v_tagctl_s 15
+#define bc_tag_addr_v_tagctl_v 16
+#define bc_tag_addr_v_tag_p 17
+#define bc_tag_addr_s_bc_tag 19
+#define bc_tag_addr_v_bc_tag 20
+// ibox and icache registers.
+#define aster_v_kar 0
+#define aster_v_ear 1
+#define aster_v_sar 2
+#define aster_v_uar 3
+#define astrr_v_kar 0
+#define astrr_v_ear 1
+#define astrr_v_sar 2
+#define astrr_v_uar 3
+#define exc_addr_v_pal 0
+#define exc_sum_v_swc 10
+#define exc_sum_v_inv 11
+#define exc_sum_v_dze 12
+#define exc_sum_v_fov 13
+#define exc_sum_v_unf 14
+#define exc_sum_v_ine 15
+#define exc_sum_v_iov 16
+#define hwint_clr_v_pc0c 27
+#define hwint_clr_v_pc1c 28
+#define hwint_clr_v_pc2c 29
+#define hwint_clr_v_crdc 32
+#define hwint_clr_v_slc 33
+// ibox and icache registers, continued
+#define icperr_stat_v_dpe 11
+#define icperr_stat_v_tpe 12
+#define icperr_stat_v_tmr 13
+#define ic_perr_stat_v_dpe 11
+#define ic_perr_stat_v_tpe 12
+#define ic_perr_stat_v_tmr 13
+#define icsr_v_pma 8
+#define icsr_v_pmp 9
+#define icsr_v_byt 17
+#define icsr_v_fmp 18
+#define icsr_v_im0 20
+#define icsr_v_im1 21
+#define icsr_v_im2 22
+#define icsr_v_im3 23
+#define icsr_v_tmm 24
+#define icsr_v_tmd 25
+#define icsr_v_fpe 26
+#define icsr_v_hwe 27
+#define icsr_s_spe 2
+#define icsr_v_spe 28
+#define icsr_v_sde 30
+#define icsr_v_crde 32
+#define icsr_v_sle 33
+#define icsr_v_fms 34
+#define icsr_v_fbt 35
+#define icsr_v_fbd 36
+#define icsr_v_dbs 37
+#define icsr_v_ista 38
+#define icsr_v_tst 39
+#define ifault_va_form_s_va 30
+#define ifault_va_form_v_va 3
+#define ifault_va_form_s_vptb 31
+#define ifault_va_form_v_vptb 33
+#define ifault_va_form_nt_s_va 19
+#define ifault_va_form_nt_v_va 3
+#define intid_s_intid 5
+#define intid_v_intid 0
+// ibox and icache registers, continued
+#define ipl_s_ipl 5
+#define ipl_v_ipl 0
+#define itb_is_s_va 30
+#define itb_is_v_va 13
+#define itb_asn_s_asn 7
+#define itb_asn_v_asn 4
+#define itb_pte_v_asm 4
+#define itb_pte_s_gh 2
+#define itb_pte_v_gh 5
+#define itb_pte_v_kre 8
+#define itb_pte_v_ere 9
+#define itb_pte_v_sre 10
+#define itb_pte_v_ure 11
+#define itb_pte_s_pfn 27
+#define itb_pte_v_pfn 32
+#define itb_pte_temp_v_asm 13
+#define itb_pte_temp_v_kre 18
+#define itb_pte_temp_v_ere 19
+#define itb_pte_temp_v_sre 20
+#define itb_pte_temp_v_ure 21
+#define itb_pte_temp_s_gh 3
+#define itb_pte_temp_v_gh 29
+#define itb_pte_temp_s_pfn 27
+#define itb_pte_temp_v_pfn 32
+// ibox and icache registers, continued
+#define itb_tag_s_va 30
+#define itb_tag_v_va 13
+#define pal_base_s_pal_base 26
+#define pal_base_v_pal_base 14
+#define pmctr_s_sel2 4
+#define pmctr_v_sel2 0
+#define pmctr_s_sel1 4
+#define pmctr_v_sel1 4
+#define pmctr_v_killk 8
+#define pmctr_v_killp 9
+#define pmctr_s_ctl2 2
+#define pmctr_v_ctl2 10
+#define pmctr_s_ctl1 2
+#define pmctr_v_ctl1 12
+#define pmctr_s_ctl0 2
+#define pmctr_v_ctl0 14
+#define pmctr_s_ctr2 14
+#define pmctr_v_ctr2 16
+#define pmctr_v_killu 30
+#define pmctr_v_sel0 31
+#define pmctr_s_ctr1 16
+#define pmctr_v_ctr1 32
+#define pmctr_s_ctr0 16
+#define pmctr_v_ctr0 48
+#define ps_v_cm0 3
+#define ps_v_cm1 4
+#define isr_s_astrr 4
+#define isr_v_astrr 0
+#define isr_s_sisr 15
+#define isr_v_sisr 4
+#define isr_v_atr 19
+#define isr_v_i20 20
+#define isr_v_i21 21
+#define isr_v_i22 22
+#define isr_v_i23 23
+#define isr_v_pc0 27
+#define isr_v_pc1 28
+#define isr_v_pc2 29
+#define isr_v_pfl 30
+#define isr_v_mck 31
+#define isr_v_crd 32
+#define isr_v_sli 33
+#define isr_v_hlt 34
+#define sirr_s_sirr 15
+#define sirr_v_sirr 4
+// ibox and icache registers, continued
+#define sl_txmit_v_tmt 7
+#define sl_rcv_v_rcv 6
+// mbox and dcache registers.
+#define alt_mode_v_am0 3
+#define alt_mode_v_am1 4
+#define cc_ctl_v_cc_ena 32
+#define dcperr_stat_v_seo 0
+#define dcperr_stat_v_lock 1
+#define dcperr_stat_v_dp0 2
+#define dcperr_stat_v_dp1 3
+#define dcperr_stat_v_tp0 4
+#define dcperr_stat_v_tp1 5
+// the following two registers are used exclusively for test and diagnostics.
+// they should not be referenced in normal operation.
+#define dc_test_ctl_v_bank0 0
+#define dc_test_ctl_v_bank1 1
+#define dc_test_ctl_v_fill_0 2
+#define dc_test_ctl_s_index 10
+#define dc_test_ctl_v_index 3
+#define dc_test_ctl_s_fill_1 19
+#define dc_test_ctl_v_fill_1 13
+#define dc_test_ctl_s_fill_2 32
+#define dc_test_ctl_v_fill_2 32
+// mbox and dcache registers, continued.
+#define dc_test_tag_v_tag_par 2
+#define dc_test_tag_v_ow0 11
+#define dc_test_tag_v_ow1 12
+#define dc_test_tag_s_tag 26
+#define dc_test_tag_v_tag 13
+#define dc_test_tag_temp_v_tag_par 2
+#define dc_test_tag_temp_v_d0p0 3
+#define dc_test_tag_temp_v_d0p1 4
+#define dc_test_tag_temp_v_d1p0 5
+#define dc_test_tag_temp_v_d1p1 6
+#define dc_test_tag_temp_v_ow0 11
+#define dc_test_tag_temp_v_ow1 12
+#define dc_test_tag_temp_s_tag 26
+#define dc_test_tag_temp_v_tag 13
+#define dtb_asn_s_asn 7
+#define dtb_asn_v_asn 57
+#define dtb_cm_v_cm0 3
+#define dtb_cm_v_cm1 4
+#define dtbis_s_va0 30
+#define dtbis_v_va0 13
+#define dtb_pte_v_for 1
+#define dtb_pte_v_fow 2
+#define dtb_pte_v_asm 4
+#define dtb_pte_s_gh 2
+#define dtb_pte_v_gh 5
+#define dtb_pte_v_kre 8
+#define dtb_pte_v_ere 9
+#define dtb_pte_v_sre 10
+#define dtb_pte_v_ure 11
+#define dtb_pte_v_kwe 12
+#define dtb_pte_v_ewe 13
+#define dtb_pte_v_swe 14
+#define dtb_pte_v_uwe 15
+#define dtb_pte_s_pfn 27
+#define dtb_pte_v_pfn 32
+// mbox and dcache registers, continued.
+#define dtb_pte_temp_v_for 0
+#define dtb_pte_temp_v_fow 1
+#define dtb_pte_temp_v_kre 2
+#define dtb_pte_temp_v_ere 3
+#define dtb_pte_temp_v_sre 4
+#define dtb_pte_temp_v_ure 5
+#define dtb_pte_temp_v_kwe 6
+#define dtb_pte_temp_v_ewe 7
+#define dtb_pte_temp_v_swe 8
+#define dtb_pte_temp_v_uwe 9
+#define dtb_pte_temp_v_asm 10
+#define dtb_pte_temp_s_fill_0 2
+#define dtb_pte_temp_v_fill_0 11
+#define dtb_pte_temp_s_pfn 27
+#define dtb_pte_temp_v_pfn 13
+#define dtb_tag_s_va 30
+#define dtb_tag_v_va 13
+// most mcsr bits are used for testability and diagnostics only.
+// for normal operation, they will be supported in the following configuration:
+// split_dcache = 1, maf_nomerge = 0, wb_flush_always = 0, wb_nomerge = 0,
+// dc_ena<1:0> = 1, dc_fhit = 0, dc_bad_parity = 0
+#define mcsr_v_big_endian 0
+#define mcsr_v_sp0 1
+#define mcsr_v_sp1 2
+#define mcsr_v_mbox_sel 3
+#define mcsr_v_e_big_endian 4
+#define mcsr_v_dbg_packet_sel 5
+#define dc_mode_v_dc_ena 0
+#define dc_mode_v_dc_fhit 1
+#define dc_mode_v_dc_bad_parity 2
+#define dc_mode_v_dc_perr_dis 3
+#define dc_mode_v_dc_doa 4
+#define maf_mode_v_maf_nomerge 0
+#define maf_mode_v_wb_flush_always 1
+#define maf_mode_v_wb_nomerge 2
+#define maf_mode_v_io_nomerge 3
+#define maf_mode_v_wb_cnt_disable 4
+#define maf_mode_v_maf_arb_disable 5
+#define maf_mode_v_dread_pending 6
+#define maf_mode_v_wb_pending 7
+// mbox and dcache registers, continued.
+#define mm_stat_v_wr 0
+#define mm_stat_v_acv 1
+#define mm_stat_v_for 2
+#define mm_stat_v_fow 3
+#define mm_stat_v_dtb_miss 4
+#define mm_stat_v_bad_va 5
+#define mm_stat_s_ra 5
+#define mm_stat_v_ra 6
+#define mm_stat_s_opcode 6
+#define mm_stat_v_opcode 11
+#define mvptbr_s_vptb 31
+#define mvptbr_v_vptb 33
+#define va_form_s_va 30
+#define va_form_v_va 3
+#define va_form_s_vptb 31
+#define va_form_v_vptb 33
+#define va_form_nt_s_va 19
+#define va_form_nt_v_va 3
+//.endm
+
+#endif
diff --git a/system/alpha/h/ev5_impure.h b/system/alpha/h/ev5_impure.h
new file mode 100644
index 000000000..88634a7ef
--- /dev/null
+++ b/system/alpha/h/ev5_impure.h
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef EV5_IMPURE_INCLUDED
+#define EV5_IMPURE_INCLUDED
+
+// This uses the Hudson file format from "impure.h" but with the fields from
+// the distrubuted palcode "ev5_impure.sdl" .. pboyle Nov/95
+
+// file: impure.sdl
+//
+// PAL impure scratch area and logout area data structure definitions for
+// Alpha firmware.
+//
+//
+// module $pal_impure;
+//
+// Edit Date Who Description
+// ---- --------- --- ---------------------
+// 1 7-Jul-93 JEM Initial Entry
+// 2 18-nov-93 JEM Add shadow bc_ctl and pmctr_ctl to impure area
+// Delete mvptbr
+// Calculate pal$logout from end of impure area
+// 3 6-dec-93 JEM Add pmctr_ctl bitfield definitions
+// 4 3-feb-94 JEM Remove f31,r31 from impure area; Remove bc_ctl,
+// pmctr_ctl; add ic_perr_stat, pmctr, dc_perr_stat,
+// sc_stat, sc_addr, sc_ctl, bc_tag_addr, ei_stat,
+// ei_addr, fill_syn, ld_lock
+// 5 19-feb-94 JEM add gpr constants, and add f31,r31 back in to be
+// consistent with ev4
+// add cns$ipr_offset
+// 6 18-apr-94 JEM Add shadow bc_ctl and pmctr_ctl to impure area again.
+// 7 18-jul-94 JEM Add bc_config shadow. Add mchk$sys_base constant
+// to mchk logout frame
+//
+//
+// constant REVISION equals 7 prefix IMPURE$; // Revision number of this file
+//orig
+
+/*
+** Macros for saving/restoring data to/from the PAL impure scratch
+** area.
+**
+** The console save state area is larger than the addressibility
+** of the HW_LD/ST instructions (10-bit signed byte displacement),
+** so some adjustments to the base offsets, as well as the offsets
+** within each base region, are necessary.
+**
+** The console save state area is divided into two segments; the
+** CPU-specific segment and the platform-specific segment. The
+** state that is saved in the CPU-specific segment includes GPRs,
+** FPRs, IPRs, halt code, MCHK flag, etc. All other state is saved
+** in the platform-specific segment.
+**
+** The impure pointer will need to be adjusted by a different offset
+** value for each region within a given segment. The SAVE and RESTORE
+** macros will auto-magically adjust the offsets accordingly.
+**
+*/
+//#define SEXT10(X) (((X) & 0x200) ? ((X) | 0xfffffffffffffc00) : (X))
+#define SEXT10(X) ((X) & 0x3ff)
+//#define SEXT10(X) (((X) << 55) >> 55)
+
+#define SAVE_GPR(reg,offset,base) \
+ stq_p reg, (SEXT10(offset-0x200))(base)
+
+#define RESTORE_GPR(reg,offset,base) \
+ ldq_p reg, (SEXT10(offset-0x200))(base)
+
+
+#define SAVE_FPR(reg,offset,base) \
+ stt reg, (SEXT10(offset-0x200))(base)
+
+#define RESTORE_FPR(reg,offset,base) \
+ ldt reg, (SEXT10(offset-0x200))(base)
+
+#define SAVE_IPR(reg,offset,base) \
+ mfpr v0, reg; \
+ stq_p v0, (SEXT10(offset-CNS_Q_IPR))(base)
+
+#define RESTORE_IPR(reg,offset,base) \
+ ldq_p v0, (SEXT10(offset-CNS_Q_IPR))(base); \
+ mtpr v0, reg
+
+#define SAVE_SHADOW(reg,offset,base) \
+ stq_p reg, (SEXT10(offset-CNS_Q_IPR))(base)
+
+#define RESTORE_SHADOW(reg,offset,base)\
+ ldq_p reg, (SEXT10(offset-CNS_Q_IPR))(base)
+
+/* Structure of the processor-specific impure area */
+
+/* aggregate impure struct prefix "" tag "";
+ * cns$flag quadword;
+ * cns$hlt quadword;
+ */
+
+/* Define base for debug monitor compatibility */
+#define CNS_Q_BASE 0x000
+#define CNS_Q_FLAG 0x100
+#define CNS_Q_HALT 0x108
+
+
+/* constant (
+ * cns$r0,cns$r1,cns$r2,cns$r3,cns$r4,cns$r5,cns$r6,cns$r7,
+ * cns$r8,cns$r9,cns$r10,cns$r11,cns$r12,cns$r13,cns$r14,cns$r15,
+ * cns$r16,cns$r17,cns$r18,cns$r19,cns$r20,cns$r21,cns$r22,cns$r23,
+ * cns$r24,cns$r25,cns$r26,cns$r27,cns$r28,cns$r29,cns$r30,cns$r31
+ * ) equals . increment 8 prefix "" tag "";
+ * cns$gpr quadword dimension 32;
+ */
+
+/* Offset to base of saved GPR area - 32 quadword */
+#define CNS_Q_GPR 0x110
+#define cns_gpr CNS_Q_GPR
+
+/* constant (
+ * cns$f0,cns$f1,cns$f2,cns$f3,cns$f4,cns$f5,cns$f6,cns$f7,
+ * cns$f8,cns$f9,cns$f10,cns$f11,cns$f12,cns$f13,cns$f14,cns$f15,
+ * cns$f16,cns$f17,cns$f18,cns$f19,cns$f20,cns$f21,cns$f22,cns$f23,
+ * cns$f24,cns$f25,cns$f26,cns$f27,cns$f28,cns$f29,cns$f30,cns$f31
+ * ) equals . increment 8 prefix "" tag "";
+ * cns$fpr quadword dimension 32;
+ */
+
+/* Offset to base of saved FPR area - 32 quadwords */
+#define CNS_Q_FPR 0x210
+
+/* #t=.;
+ * cns$mchkflag quadword;
+ */
+#define CNS_Q_MCHK 0x310
+
+/* constant cns$pt_offset equals .;
+ * constant (
+ * cns$pt0,cns$pt1,cns$pt2,cns$pt3,cns$pt4,cns$pt5,cns$pt6,
+ * cns$pt7,cns$pt8,cns$pt9,cns$pt10,cns$pt11,cns$pt12,cns$pt13,
+ * cns$pt14,cns$pt15,cns$pt16,cns$pt17,cns$pt18,cns$pt19,cns$pt20,
+ * cns$pt21,cns$pt22,cns$pt23
+ * ) equals . increment 8 prefix "" tag "";
+ * cns$pt quadword dimension 24;
+ */
+/* Offset to base of saved PALtemp area - 25 quadwords */
+#define CNS_Q_PT 0x318
+
+/* cns$shadow8 quadword;
+ * cns$shadow9 quadword;
+ * cns$shadow10 quadword;
+ * cns$shadow11 quadword;
+ * cns$shadow12 quadword;
+ * cns$shadow13 quadword;
+ * cns$shadow14 quadword;
+ * cns$shadow25 quadword;
+ */
+/* Offset to base of saved PALshadow area - 8 quadwords */
+#define CNS_Q_SHADOW 0x3D8
+
+/* Offset to base of saved IPR area */
+#define CNS_Q_IPR 0x418
+
+/* constant cns$ipr_offset equals .; */
+/* cns$exc_addr quadword; */
+#define CNS_Q_EXC_ADDR 0x418
+/* cns$pal_base quadword; */
+#define CNS_Q_PAL_BASE 0x420
+/* cns$mm_stat quadword; */
+#define CNS_Q_MM_STAT 0x428
+/* cns$va quadword; */
+#define CNS_Q_VA 0x430
+/* cns$icsr quadword; */
+#define CNS_Q_ICSR 0x438
+/* cns$ipl quadword; */
+#define CNS_Q_IPL 0x440
+/* cns$ps quadword; // Ibox current mode */
+#define CNS_Q_IPS 0x448
+/* cns$itb_asn quadword; */
+#define CNS_Q_ITB_ASN 0x450
+/* cns$aster quadword; */
+#define CNS_Q_ASTER 0x458
+/* cns$astrr quadword; */
+#define CNS_Q_ASTRR 0x460
+/* cns$isr quadword; */
+#define CNS_Q_ISR 0x468
+/* cns$ivptbr quadword; */
+#define CNS_Q_IVPTBR 0x470
+/* cns$mcsr quadword; */
+#define CNS_Q_MCSR 0x478
+/* cns$dc_mode quadword; */
+#define CNS_Q_DC_MODE 0x480
+/* cns$maf_mode quadword; */
+#define CNS_Q_MAF_MODE 0x488
+/* cns$sirr quadword; */
+#define CNS_Q_SIRR 0x490
+/* cns$fpcsr quadword; */
+#define CNS_Q_FPCSR 0x498
+/* cns$icperr_stat quadword; */
+#define CNS_Q_ICPERR_STAT 0x4A0
+/* cns$pmctr quadword; */
+#define CNS_Q_PM_CTR 0x4A8
+/* cns$exc_sum quadword; */
+#define CNS_Q_EXC_SUM 0x4B0
+/* cns$exc_mask quadword; */
+#define CNS_Q_EXC_MASK 0x4B8
+/* cns$intid quadword; */
+#define CNS_Q_INT_ID 0x4C0
+/* cns$dcperr_stat quadword; */
+#define CNS_Q_DCPERR_STAT 0x4C8
+/* cns$sc_stat quadword; */
+#define CNS_Q_SC_STAT 0x4D0
+/* cns$sc_addr quadword; */
+#define CNS_Q_SC_ADDR 0x4D8
+/* cns$sc_ctl quadword; */
+#define CNS_Q_SC_CTL 0x4E0
+/* cns$bc_tag_addr quadword; */
+#define CNS_Q_BC_TAG_ADDR 0x4E8
+/* cns$ei_stat quadword; */
+#define CNS_Q_EI_STAT 0x4F0
+/* cns$ei_addr quadword; */
+#define CNS_Q_EI_ADDR 0x4F8
+/* cns$fill_syn quadword; */
+#define CNS_Q_FILL_SYN 0x500
+/* cns$ld_lock quadword; */
+#define CNS_Q_LD_LOCK 0x508
+/* cns$bc_ctl quadword; // shadow of on chip bc_ctl */
+#define CNS_Q_BC_CTL 0x510
+/* cns$pmctr_ctl quadword; // saved frequency select info for performance monitor counter */
+#define CNS_Q_PM_CTL 0x518
+/* cns$bc_config quadword; // shadow of on chip bc_config */
+#define CNS_Q_BC_CFG 0x520
+
+/* constant cns$size equals .;
+ *
+ * constant pal$impure_common_size equals (%x0200 +7) & %xfff8;
+ * constant pal$impure_specific_size equals (.+7) & %xfff8;
+ * constant cns$mchksize equals (.+7-#t) & %xfff8;
+ * constant pal$logout_area equals pal$impure_specific_size ;
+ * end impure;
+*/
+
+/* This next set of stuff came from the old code ..pb */
+#define CNS_Q_SROM_REV 0x528
+#define CNS_Q_PROC_ID 0x530
+#define CNS_Q_MEM_SIZE 0x538
+#define CNS_Q_CYCLE_CNT 0x540
+#define CNS_Q_SIGNATURE 0x548
+#define CNS_Q_PROC_MASK 0x550
+#define CNS_Q_SYSCTX 0x558
+
+
+
+#define MACHINE_CHECK_CRD_BASE 0
+#define MACHINE_CHECK_SIZE ((CNS_Q_SYSCTX + 7 - CNS_Q_MCHK) & 0xfff8)
+
+
+
+/*
+ * aggregate EV5PMCTRCTL_BITS structure fill prefix PMCTR_CTL$;
+ * SPROCESS bitfield length 1 ;
+ * FILL_0 bitfield length 3 fill tag $$;
+ * FRQ2 bitfield length 2 ;
+ * FRQ1 bitfield length 2 ;
+ * FRQ0 bitfield length 2 ;
+ * CTL2 bitfield length 2 ;
+ * CTL1 bitfield length 2 ;
+ * CTL0 bitfield length 2 ;
+ * FILL_1 bitfield length 16 fill tag $$;
+ * FILL_2 bitfield length 32 fill tag $$;
+ * end EV5PMCTRCTL_BITS;
+ *
+ * end_module $pal_impure;
+ *
+ * module $pal_logout;
+ *
+ * //
+ * // Start definition of Corrected Error Frame
+ * //
+ */
+
+/*
+ * aggregate crd_logout struct prefix "" tag "";
+ */
+
+#define pal_logout_area 0x600
+#define mchk_crd_base 0
+
+/* mchk$crd_flag quadword; */
+#define mchk_crd_flag 0
+/* mchk$crd_offsets quadword; */
+#define mchk_crd_offsets 8
+/*
+ * // Pal-specific information */
+#define mchk_crd_mchk_code 0x10
+/* mchk$crd_mchk_code quadword;
+ *
+ * // CPU-specific information
+ * constant mchk$crd_cpu_base equals . ;
+ * mchk$crd_ei_addr quadword; */
+#define mchk_crd_ei_addr 0x18
+/* mchk$crd_fill_syn quadword; */
+#define mchk_crd_fill_syn 0x20
+/* mchk$crd_ei_stat quadword; */
+#define mchk_crd_ei_stat 0x28
+/* mchk$crd_isr quadword; */
+#define mchk_crd_isr 0x30
+
+/*
+ * Hacked up constants for the turbolaser build. Hope
+ * this is moreless correct
+ */
+
+#define mchk_crd_whami 0x38
+#define mchk_crd_tldev 0x40
+#define mchk_crd_tlber 0x48
+#define mchk_crd_tlesr0 0x50
+#define mchk_crd_tlesr1 0x58
+#define mchk_crd_tlesr2 0x60
+#define mchk_crd_tlesr3 0x68
+#define mchk_crd_rsvd 0x70
+
+
+/*
+ * mchk area seems different for tlaser
+ */
+
+#define mchk_crd_size 0x80
+#define mchk_mchk_base (mchk_crd_size)
+
+#define mchk_tlber 0x0
+#define mchk_tlepaerr 0x8
+#define mchk_tlepderr 0x10
+#define mchk_tlepmerr 0x18
+
+
+/*
+ * // System-specific information
+ * constant mchk$crd_sys_base equals . ;
+ * constant mchk$crd_size equals (.+7) & %xfff8;
+ *
+ * end crd_logout;
+ * //
+ * // Start definition of Machine check logout Frame
+ * //
+ * aggregate logout struct prefix "" tag "";
+ * mchk$flag quadword; */
+/* mchk$offsets quadword; */
+/*
+ * // Pal-specific information
+ * mchk$mchk_code quadword; */
+/*
+
+ * mchk$pt quadword dimension 24;
+ *
+ * // CPU-specific information
+ * constant mchk$cpu_base equals . ;
+ * mchk$exc_addr quadword;
+ * mchk$exc_sum quadword;
+ * mchk$exc_mask quadword;
+ * mchk$pal_base quadword;
+ * mchk$isr quadword;
+ * mchk$icsr quadword;
+ * mchk$ic_perr_stat quadword;
+ * mchk$dc_perr_stat quadword;
+ * mchk$va quadword;
+ * mchk$mm_stat quadword;
+ * mchk$sc_addr quadword;
+ * mchk$sc_stat quadword;
+ * mchk$bc_tag_addr quadword;
+ * mchk$ei_addr quadword;
+ * mchk$fill_syn quadword;
+ * mchk$ei_stat quadword;
+ * mchk$ld_lock quadword;
+ *
+ * // System-specific information
+ *
+ * constant mchk$sys_base equals . ;
+ * mchk$sys_ipr1 quadword ; // Holder for system-specific stuff
+ *
+ * constant mchk$size equals (.+7) & %xfff8;
+ *
+ *
+ * constant mchk$crd_base equals 0 ;
+ * constant mchk$mchk_base equals mchk$crd_size ;
+ *
+ *
+ * end logout;
+ *
+ * end_module $pal_logout;
+*/
+
+/*
+ * this is lingering in the old ladbx code but looks like it was from
+ * ev4 days. This was 0x160 in the old days..pb
+ */
+#define LAF_K_SIZE MACHINE_CHECK_SIZE
+#endif
diff --git a/system/alpha/h/ev5_osfalpha_defs.h b/system/alpha/h/ev5_osfalpha_defs.h
new file mode 100644
index 000000000..bb98503b4
--- /dev/null
+++ b/system/alpha/h/ev5_osfalpha_defs.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef EV5_OSFALPHA_DEFS_INCLUDED
+#define EV5_OSFALPHA_DEFS_INCLUDED 1
+
+// from ev5_osfalpha_defs.mar from Lance's fetch directory
+// lowercaseified and $ changed to _ and reformatting for gas...pb Nov/95
+
+//
+// PS Layout - PS
+// Loc Size name function
+// ------ ------ ----- -----------------------------------
+// <0:2> 3 IPL Prio level
+// <3> 1 CM Current Mode
+//
+
+#define osfps_v_mode 3
+#define osfps_m_mode (1<<osfps_v_mode)
+#define osfps_v_ipl 0
+#define osfps_m_ipl (7<<osfps_v_ipl)
+
+#define osfipl_c_mchk 7
+#define osfipl_c_rt 6
+#define osfipl_c_clk 5
+#define osfipl_c_dev1 4
+#define osfipl_c_dev0 3
+#define osfipl_c_sw1 2
+#define osfipl_c_sw0 1
+#define osfipl_c_zero 0
+
+#define osfint_c_mchk 2
+#define osfint_c_clk 1
+#define osfint_c_dev 3
+#define osfint_c_ip 0
+#define osfint_c_perf 4
+#define osfint_c_passrel 5
+
+//
+// PTE layout - symbol prefix osfpte_
+//
+// Loc Size name function
+// ------ ------ ------ -----------------------------------
+// <63:32> 32 PFN Page Frame Number
+// <31:16> 16 SOFT Bits reserved for software use
+// <15:14> 2
+// <13> 1 UWE User write enable
+// <12> 1 KWE Kernel write enable
+// <11:10> 2
+// <9> 1 URE User read enable
+// <8> 1 KRE Kernel read enable
+// <7:6> 2 RES Reserved SBZ
+// <5> 1 HPF Huge Page Flag
+// <4> 1 ASM Wild card address space number match
+// <3> 1 FOE Fault On execute
+// <2> 1 FOW Fault On Write
+// <1> 1 FOR Fault On Read
+// <0> 1 V valid bit
+//
+
+#define osfpte_v_pfn 32
+#define osfpte_m_soft (0xFFFF0000)
+#define osfpte_v_soft 16
+#define osfpte_m_uwe (0x2000)
+#define osfpte_v_uwe 13
+#define osfpte_m_kwe (0x1000)
+#define osfpte_v_kwe 12
+#define osfpte_m_ure (0x0200)
+#define osfpte_v_ure 9
+#define osfpte_m_kre (0x0100)
+#define osfpte_v_kre 8
+#define osfpte_m_hpf (0x0020)
+#define osfpte_v_hpf 5
+#define osfpte_m_asm (0x0010)
+#define osfpte_v_asm 4
+#define osfpte_m_foe (0x0008)
+#define osfpte_v_foe 3
+#define osfpte_m_fow (0x0004)
+#define osfpte_v_fow 2
+#define osfpte_m_for (0x0002)
+#define osfpte_v_for 1
+#define osfpte_m_v (0x0001)
+#define osfpte_v_v 0
+
+#define osfpte_m_ksegbits (osfpte_m_kre | osfpte_m_kwe | osfpte_m_v | osfpte_m_asm)
+#define osfpte_m_prot (osfpte_m_ure+osfpte_m_uwe | osfpte_m_kre | osfpte_m_kwe)
+
+//
+// VA layout - symbol prefix VA_
+//
+// Loc Size name function
+// ------ ------ ------- -----------------------------------
+// <42:33> 10 SEG1 First seg table offset for mapping
+// <32:23> 10 SEG2 Second seg table offset for mapping
+// <22:13> 10 SEG3 Third seg table offset for mapping
+// <12:0> 13 OFFSET Byte within page
+//
+
+#define osfva_m_offset (0x000000001FFF)
+#define osfva_v_offset 0
+#define osfva_m_seg3 (0x0000007FE000)
+#define osfva_v_seg3 13
+#define osfva_m_seg2 (0x0001FF800000)
+#define osfva_v_seg2 23
+#define osfva_m_seg1 (0x7FE00000000)
+#define osfva_v_seg1 33
+
+#define osfpcb_q_ksp (0x0000)
+#define osfpcb_q_usp (0x0008)
+#define osfpcb_q_Usp (0x0008)
+#define osfpcb_q_mmptr (0x0010)
+#define osfpcb_q_Mmptr (0x0010)
+#define osfpcb_l_cc (0x0018)
+#define osfpcb_l_asn (0x001C)
+#define osfpcb_q_unique (0x0020)
+#define osfpcb_q_fen (0x0028)
+#define osfpcb_v_pme 62
+
+#define osfsf_ps (0x00)
+#define osfsf_pc (0x08)
+#define osfsf_gp (0x10)
+#define osfsf_a0 (0x18)
+#define osfsf_a1 (0x20)
+#define osfsf_a2 (0x28)
+#define osfsf_c_size (0x30)
+
+#endif
diff --git a/system/alpha/h/ev5_paldef.h b/system/alpha/h/ev5_paldef.h
new file mode 100644
index 000000000..49cea5faa
--- /dev/null
+++ b/system/alpha/h/ev5_paldef.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 1993 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef EV5_PALDEF_INCLUDED
+#define EV5_PALDEF_INCLUDED 1
+
+// from ev5_paldef.mar from Lance's fetch directory...pb Nov/95
+// some entries have been superceeded by the more recent evt_defs.h
+
+// These are lower-caseified and have the $ signs (unnecessarily we
+// now discover) removed.
+
+// Note that at the bottom of this file is the version of ev5_defs.mar
+// which is more recent than the top part of the file and contains
+// overlapping information...pb Nov/95
+
+#define hlt_c_reset 0
+#define hlt_c_hw_halt 1
+#define hlt_c_ksp_inval 2
+#define hlt_c_scbb_inval 3
+#define hlt_c_ptbr_inval 4
+#define hlt_c_sw_halt 5
+#define hlt_c_dbl_mchk 6
+#define hlt_c_mchk_from_pal 7
+#define hlt_c_start 32
+#define hlt_c_callback 33
+#define hlt_c_mpstart 34
+#define hlt_c_lfu_start 35
+
+#define mchk_c_tperr (64<<1)
+#define mchk_c_tcperr (65<<1)
+#define mchk_c_herr (66<<1)
+#define mchk_c_ecc_c (67<<1)
+#define mchk_c_ecc_nc (68<<1)
+#define mchk_c_unknown (69<<1)
+#define mchk_c_cacksoft (70<<1)
+#define mchk_c_bugcheck (71<<1)
+#define mchk_c_os_bugcheck (72<<1)
+#define mchk_c_dcperr (73<<1)
+#define mchk_c_icperr (74<<1)
+#define mchk_c_retryable_ird (75<<1)
+#define mchk_c_proc_hrd_error (76<<1)
+#define mchk_c_scperr (77<<1)
+#define mchk_c_bcperr (78<<1)
+//; mchk codes above 255 reserved for platform specific errors
+
+
+#define mchk_c_read_nxm (256<<1)
+#define mchk_c_sys_hrd_error (257<<1)
+#define mchk_c_sys_ecc (258<<1)
+
+#define page_seg_size_bits 10
+#define page_offset_size_bits 13
+#define page_size_bytes 8192
+#define va_size_bits 43
+#define pa_size_bits 45
+
+// replaced by ev5_defs.h #define pt0 (0x140)
+// replaced by ev5_defs.h #define pt1 (0x141)
+// replaced by ev5_defs.h #define pt2 (0x142)
+#define pt_entuna (0x142)
+// replaced by ev5_defs.h #define pt3 (0x143)
+#define pt_impure (0x143)
+// replaced by ev5_defs.h #define pt4 (0x144)
+// replaced by ev5_defs.h #define pt5 (0x145)
+// replaced by ev5_defs.h #define pt6 (0x146)
+// replaced by ev5_defs.h #define pt7 (0x147)
+#define pt_entif (0x147)
+// replaced by ev5_defs.h #define pt8 (0x148)
+#define pt_intmask (0x148)
+// replaced by ev5_defs.h #define pt9 (0x149)
+#define pt_entsys (0x149)
+#define pt_ps (0x149)
+// replaced by ev5_defs.h #define pt10 (0x14a)
+// replaced by ev5_defs.h #define pt11 (0x14b)
+#define pt_trap (0x14b)
+#define pt_entint (0x14b)
+// replaced by ev5_defs.h #define pt12 (0x14c)
+#define pt_entarith (0x14c)
+// replaced by ev5_defs.h #define pt13 (0x14d)
+#define pt_sys0 (0x14d)
+// replaced by ev5_defs.h #define pt14 (0x14e)
+#define pt_sys1 (0x14e)
+// replaced by ev5_defs.h #define pt15 (0x14f)
+#define pt_sys2 (0x14f)
+// replaced by ev5_defs.h #define pt16 (0x150)
+#define pt_whami (0x150)
+#define pt_mces (0x150)
+#define pt_misc (0x150)
+// replaced by ev5_defs.h #define pt17 (0x151)
+#define pt_scc (0x151)
+#define pt_sysval (0x151)
+// replaced by ev5_defs.h #define pt18 (0x152)
+#define pt_prbr (0x152)
+#define pt_usp (0x152)
+// replaced by ev5_defs.h #define pt19 (0x153)
+#define pt_ksp (0x153)
+// replaced by ev5_defs.h #define pt20 (0x154)
+#define pt_ptbr (0x154)
+// replaced by ev5_defs.h #define pt21 (0x155)
+#define pt_vptbr (0x155)
+#define pt_entmm (0x155)
+// replaced by ev5_defs.h #define pt22 (0x156)
+#define pt_scbb (0x156)
+#define pt_kgp (0x156)
+// replaced by ev5_defs.h #define pt23 (0x157)
+#define pt_pcbb (0x157)
+
+
+#define pt_misc_v_switch 48
+#define pt_misc_v_cm 56
+
+#define mmcsr_c_tnv 0
+#define mmcsr_c_acv 1
+#define mmcsr_c_for 2
+#define mmcsr_c_foe 3
+#define mmcsr_c_fow 4
+
+#define mm_stat_m_opcode (0x3F)
+#define mm_stat_m_ra (0x1F)
+#define evx_opc_sync (0x18)
+#define EVX_OPC_SYNC (0x18)
+#define evx_opc_hw_ld (0x1B)
+
+#define osf_a0_bpt (0x0)
+#define osf_a0_bugchk (0x1)
+#define osf_a0_gentrap (0x2)
+#define osf_a0_fen (0x3)
+#define osf_a0_opdec (0x4)
+
+#define ipl_machine_check 31
+#define ipl_powerfail 30
+#define ipl_perf_count 29
+#define ipl_clock 22
+#define ipl_interprocessor 22
+
+#endif
diff --git a/system/alpha/h/fromHudsonMacros.h b/system/alpha/h/fromHudsonMacros.h
new file mode 100644
index 000000000..68f8999c0
--- /dev/null
+++ b/system/alpha/h/fromHudsonMacros.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 1993-1994 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef HUDSON_MACROS_LOADED
+#define HUDSON_MACROS_LOADED 1
+
+#define STALL \
+ mfpr r31, pt0
+
+#define NOP \
+ bis $31, $31, $31
+
+/*
+** Align code on an 8K byte page boundary.
+*/
+
+#define ALIGN_PAGE \
+ .align 13
+
+/*
+** Align code on a 32 byte block boundary.
+*/
+
+#define ALIGN_BLOCK \
+ .align 5
+
+/*
+** Align code on a quadword boundary.
+*/
+
+#define ALIGN_BRANCH \
+ .align 3
+
+/*
+** Hardware vectors go in .text 0 sub-segment.
+*/
+
+#define HDW_VECTOR(offset) \
+ . = offset
+
+/*
+** Privileged CALL_PAL functions are in .text 1 sub-segment.
+*/
+
+#define CALL_PAL_PRIV(vector) \
+ . = (PAL_CALL_PAL_PRIV_ENTRY+(vector<<6))
+
+/*
+** Unprivileged CALL_PAL functions are in .text 1 sub-segment,
+** the privileged bit is removed from these vectors.
+*/
+
+#define CALL_PAL_UNPRIV(vector) \
+ . = (PAL_CALL_PAL_UNPRIV_ENTRY+((vector&0x3F)<<6))
+
+/*
+** Implements a load "immediate" longword function
+*/
+#define LDLI(reg,val) \
+ ldah reg, ((val+0x8000) >> 16)(zero); \
+ lda reg, (val&0xffff)(reg)
+
+#endif
diff --git a/system/alpha/h/fromHudsonOsf.h b/system/alpha/h/fromHudsonOsf.h
new file mode 100644
index 000000000..e1dfc8171
--- /dev/null
+++ b/system/alpha/h/fromHudsonOsf.h
@@ -0,0 +1,483 @@
+/*
+ * Copyright (c) 1993-1994 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FROMHUDSONOSF_INCLUDED
+#define FROMHUDSONOSF_INCLUDED 1
+
+#define __OSF_LOADED 1
+/*
+** Seg0 and Seg1 Virtual Address (VA) Format
+**
+** Loc Size Name Function
+** ----- ---- ---- ---------------------------------
+** <42:33> 10 SEG1 First level page table offset
+** <32:23> 10 SEG2 Second level page table offset
+** <22:13> 10 SEG3 Third level page table offset
+** <12:00> 13 OFFSET Byte within page offset
+*/
+
+#define VA_V_SEG1 33
+#define VA_M_SEG1 (0x3FF<<VA_V_SEG1)
+#define VA_V_SEG2 23
+#define VA_M_SEG2 (0x3FF<<VA_V_SEG2)
+#define VA_V_SEG3 13
+#define VA_M_SEG3 (0x3FF<<VA_V_SEG3)
+#define VA_V_OFFSET 0
+#define VA_M_OFFSET 0x1FFF
+
+/*
+** Virtual Address Options: 8K byte page size
+*/
+
+#define VA_S_SIZE 43
+#define VA_S_OFF 13
+#define va_s_off 13
+#define VA_S_SEG 10
+#define VA_S_PAGE_SIZE 8192
+
+/*
+** Page Table Entry (PTE) Format
+**
+** Extent Size Name Function
+** ------ ---- ---- ---------------------------------
+** <63:32> 32 PFN Page Frame Number
+** <31:16> 16 SW Reserved for software
+** <15:14> 2 RSV0 Reserved for hardware SBZ
+** <13> 1 UWE User Write Enable
+** <12> 1 KWE Kernel Write Enable
+** <11:10> 2 RSV1 Reserved for hardware SBZ
+** <9> 1 URE User Read Enable
+** <8> 1 KRE Kernel Read Enable
+** <7> 1 RSV2 Reserved for hardware SBZ
+** <6:5> 2 GH Granularity Hint
+** <4> 1 ASM Address Space Match
+** <3> 1 FOE Fault On Execute
+** <2> 1 FOW Fault On Write
+** <1> 1 FOR Fault On Read
+** <0> 1 V Valid
+*/
+
+#define PTE_V_PFN 32
+#define PTE_M_PFN 0xFFFFFFFF00000000
+#define PTE_V_SW 16
+#define PTE_M_SW 0x00000000FFFF0000
+#define PTE_V_UWE 13
+#define PTE_M_UWE (1<<PTE_V_UWE)
+#define PTE_V_KWE 12
+#define PTE_M_KWE (1<<PTE_V_KWE)
+#define PTE_V_URE 9
+#define PTE_M_URE (1<<PTE_V_URE)
+#define PTE_V_KRE 8
+#define PTE_M_KRE (1<<PTE_V_KRE)
+#define PTE_V_GH 5
+#define PTE_M_GH (3<<PTE_V_GH)
+#define PTE_V_ASM 4
+#define PTE_M_ASM (1<<PTE_V_ASM)
+#define PTE_V_FOE 3
+#define PTE_M_FOE (1<<PTE_V_FOE)
+#define PTE_V_FOW 2
+#define PTE_M_FOW (1<<PTE_V_FOW)
+#define PTE_V_FOR 1
+#define PTE_M_FOR (1<<PTE_V_FOR)
+#define PTE_V_VALID 0
+#define PTE_M_VALID (1<<PTE_V_VALID)
+
+#define PTE_M_KSEG 0x1111
+#define PTE_M_PROT 0x3300
+#define pte_m_prot 0x3300
+
+/*
+** System Entry Instruction Fault (entIF) Constants:
+*/
+
+#define IF_K_BPT 0x0
+#define IF_K_BUGCHK 0x1
+#define IF_K_GENTRAP 0x2
+#define IF_K_FEN 0x3
+#define IF_K_OPCDEC 0x4
+
+/*
+** System Entry Hardware Interrupt (entInt) Constants:
+*/
+
+#define INT_K_IP 0x0
+#define INT_K_CLK 0x1
+#define INT_K_MCHK 0x2
+#define INT_K_DEV 0x3
+#define INT_K_PERF 0x4
+
+/*
+** System Entry MM Fault (entMM) Constants:
+*/
+
+#define MM_K_TNV 0x0
+#define MM_K_ACV 0x1
+#define MM_K_FOR 0x2
+#define MM_K_FOE 0x3
+#define MM_K_FOW 0x4
+
+/*
+** Process Control Block (PCB) Offsets:
+*/
+
+#define PCB_Q_KSP 0x0000
+#define PCB_Q_USP 0x0008
+#define PCB_Q_PTBR 0x0010
+#define PCB_L_PCC 0x0018
+#define PCB_L_ASN 0x001C
+#define PCB_Q_UNIQUE 0x0020
+#define PCB_Q_FEN 0x0028
+#define PCB_Q_RSV0 0x0030
+#define PCB_Q_RSV1 0x0038
+
+/*
+** Processor Status Register (PS) Bit Summary
+**
+** Extent Size Name Function
+** ------ ---- ---- ---------------------------------
+** <3> 1 CM Current Mode
+** <2:0> 3 IPL Interrupt Priority Level
+**/
+
+#define PS_V_CM 3
+#define PS_M_CM (1<<PS_V_CM)
+#define PS_V_IPL 0
+#define PS_M_IPL (7<<PS_V_IPL)
+
+#define PS_K_KERN (0<<PS_V_CM)
+#define PS_K_USER (1<<PS_V_CM)
+
+#define IPL_K_ZERO 0x0
+#define IPL_K_SW0 0x1
+#define IPL_K_SW1 0x2
+#define IPL_K_DEV0 0x3
+#define IPL_K_DEV1 0x4
+#define IPL_K_CLK 0x5
+#define IPL_K_RT 0x6
+#define IPL_K_PERF 0x6
+#define IPL_K_PFAIL 0x6
+#define IPL_K_MCHK 0x7
+
+#define IPL_K_LOW 0x0
+#define IPL_K_HIGH 0x7
+
+/*
+** SCB Offset Definitions:
+*/
+
+#define SCB_Q_FEN 0x0010
+#define SCB_Q_ACV 0x0080
+#define SCB_Q_TNV 0x0090
+#define SCB_Q_FOR 0x00A0
+#define SCB_Q_FOW 0x00B0
+#define SCB_Q_FOE 0x00C0
+#define SCB_Q_ARITH 0x0200
+#define SCB_Q_KAST 0x0240
+#define SCB_Q_EAST 0x0250
+#define SCB_Q_SAST 0x0260
+#define SCB_Q_UAST 0x0270
+#define SCB_Q_UNALIGN 0x0280
+#define SCB_Q_BPT 0x0400
+#define SCB_Q_BUGCHK 0x0410
+#define SCB_Q_OPCDEC 0x0420
+#define SCB_Q_ILLPAL 0x0430
+#define SCB_Q_TRAP 0x0440
+#define SCB_Q_CHMK 0x0480
+#define SCB_Q_CHME 0x0490
+#define SCB_Q_CHMS 0x04A0
+#define SCB_Q_CHMU 0x04B0
+#define SCB_Q_SW0 0x0500
+#define SCB_Q_SW1 0x0510
+#define SCB_Q_SW2 0x0520
+#define SCB_Q_SW3 0x0530
+#define SCB_Q_SW4 0x0540
+#define SCB_Q_SW5 0x0550
+#define SCB_Q_SW6 0x0560
+#define SCB_Q_SW7 0x0570
+#define SCB_Q_SW8 0x0580
+#define SCB_Q_SW9 0x0590
+#define SCB_Q_SW10 0x05A0
+#define SCB_Q_SW11 0x05B0
+#define SCB_Q_SW12 0x05C0
+#define SCB_Q_SW13 0x05D0
+#define SCB_Q_SW14 0x05E0
+#define SCB_Q_SW15 0x05F0
+#define SCB_Q_CLOCK 0x0600
+#define SCB_Q_INTER 0x0610
+#define SCB_Q_SYSERR 0x0620
+#define SCB_Q_PROCERR 0x0630
+#define SCB_Q_PWRFAIL 0x0640
+#define SCB_Q_PERFMON 0x0650
+#define SCB_Q_SYSMCHK 0x0660
+#define SCB_Q_PROCMCHK 0x0670
+#define SCB_Q_PASSREL 0x0680
+
+/*
+** Stack Frame (FRM) Offsets:
+**
+** There are two types of system entries for OSF/1 - those for the
+** callsys CALL_PAL function and those for exceptions and interrupts.
+** Both entry types use the same stack frame layout. The stack frame
+** contains space for the PC, the PS, the saved GP, and the saved
+** argument registers a0, a1, and a2. On entry, SP points to the
+** saved PS.
+*/
+
+#define FRM_Q_PS 0x0000
+#define FRM_Q_PC 0x0008
+#define FRM_Q_GP 0x0010
+#define FRM_Q_A0 0x0018
+#define FRM_Q_A1 0x0020
+#define FRM_Q_A2 0x0028
+
+#define FRM_K_SIZE 48
+
+#define STACK_FRAME(tmp1,tmp2) \
+ sll ps, 63-PS_V_CM, p7; \
+ bge p7, 0f; \
+ bis zero, zero, ps; \
+ mtpr sp, ptUsp; \
+ mfpr sp, ptKsp; \
+0: lda sp, 0-FRM_K_SIZE(sp); \
+ stq tmp1, FRM_Q_PS(sp); \
+ stq tmp2, FRM_Q_PC(sp); \
+ stq gp, FRM_Q_GP(sp); \
+ stq a0, FRM_Q_A0(sp); \
+ stq a1, FRM_Q_A1(sp); \
+ stq a2, FRM_Q_A2(sp)
+
+/*
+** Halt Codes:
+*/
+
+#define HLT_K_RESET 0x0000
+#define HLT_K_HW_HALT 0x0001
+#define HLT_K_KSP_INVAL 0x0002
+#define HLT_K_SCBB_INVAL 0x0003
+#define HLT_K_PTBR_INVAL 0x0004
+#define HLT_K_SW_HALT 0x0005
+#define HLT_K_DBL_MCHK 0x0006
+#define HLT_K_MCHK_FROM_PAL 0x0007
+
+/*
+** Machine Check Codes:
+*/
+
+#define MCHK_K_TPERR 0x0080
+#define MCHK_K_TCPERR 0x0082
+#define MCHK_K_HERR 0x0084
+#define MCHK_K_ECC_C 0x0086
+#define MCHK_K_ECC_NC 0x0088
+#define MCHK_K_UNKNOWN 0x008A
+#define MCHK_K_CACKSOFT 0x008C
+#define MCHK_K_BUGCHECK 0x008E
+#define MCHK_K_OS_BUGCHECK 0x0090
+#define MCHK_K_DCPERR 0x0092
+#define MCHK_K_ICPERR 0x0094
+#define MCHK_K_RETRY_IRD 0x0096
+#define MCHK_K_PROC_HERR 0x0098
+
+/*
+** System Machine Check Codes:
+*/
+
+#define MCHK_K_READ_NXM 0x0200
+#define MCHK_K_SYS_HERR 0x0202
+
+/*
+** Machine Check Error Status Summary (MCES) Register Format
+**
+** Extent Size Name Function
+** ------ ---- ---- ---------------------------------
+** <0> 1 MIP Machine check in progress
+** <1> 1 SCE System correctable error in progress
+** <2> 1 PCE Processor correctable error in progress
+** <3> 1 DPC Disable PCE error reporting
+** <4> 1 DSC Disable SCE error reporting
+*/
+
+#define MCES_V_MIP 0
+#define MCES_M_MIP (1<<MCES_V_MIP)
+#define MCES_V_SCE 1
+#define MCES_M_SCE (1<<MCES_V_SCE)
+#define MCES_V_PCE 2
+#define MCES_M_PCE (1<<MCES_V_PCE)
+#define MCES_V_DPC 3
+#define MCES_M_DPC (1<<MCES_V_DPC)
+#define MCES_V_DSC 4
+#define MCES_M_DSC (1<<MCES_V_DSC)
+
+#define MCES_M_ALL (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \
+ | MCES_M_DSC)
+
+/*
+** Who-Am-I (WHAMI) Register Format
+**
+** Extent Size Name Function
+** ------ ---- ---- ---------------------------------
+** <7:0> 8 ID Who-Am-I identifier
+** <15:8> 1 SWAP Swap PALcode flag - character 'S'
+*/
+
+#define WHAMI_V_SWAP 8
+#define WHAMI_M_SWAP (1<<WHAMI_V_SWAP)
+#define WHAMI_V_ID 0
+#define WHAMI_M_ID 0xFF
+
+#define WHAMI_K_SWAP 0x53 /* Character 'S' */
+
+/*
+** Conventional Register Usage Definitions
+**
+** Assembler temporary `at' is `AT' so it doesn't conflict with the
+** `.set at' assembler directive.
+*/
+
+#define v0 $0 /* Function Return Value Register */
+#define t0 $1 /* Scratch (Temporary) Registers ... */
+#define t1 $2
+#define t2 $3
+#define t3 $4
+#define t4 $5
+#define t5 $6
+#define t6 $7
+#define t7 $8
+#define s0 $9 /* Saved (Non-Volatile) Registers ... */
+#define s1 $10
+#define s2 $11
+#define s3 $12
+#define s4 $13
+#define s5 $14
+#define fp $15 /* Frame Pointer Register, Or S6 */
+#define s6 $15
+#define a0 $16 /* Argument Registers ... */
+#define a1 $17
+#define a2 $18
+#define a3 $19
+#define a4 $20
+#define a5 $21
+#define t8 $22 /* Scratch (Temporary) Registers ... */
+#define t9 $23
+#define t10 $24
+#define t11 $25
+#define ra $26 /* Return Address Register */
+#define pv $27 /* Procedure Value Register, Or T12 */
+#define t12 $27
+#define AT $28 /* Assembler Temporary (Volatile) Register */
+#define gp $29 /* Global Pointer Register */
+#define sp $30 /* Stack Pointer Register */
+#define zero $31 /* Zero Register */
+
+/*
+** OSF/1 Unprivileged CALL_PAL Entry Offsets:
+**
+** Entry Name Offset (Hex)
+**
+** bpt 0080
+** bugchk 0081
+** callsys 0083
+** imb 0086
+** rdunique 009E
+** wrunique 009F
+** gentrap 00AA
+** dbgstop 00AD
+*/
+
+#define UNPRIV 0x80
+#define PAL_BPT_ENTRY 0x80
+#define PAL_BUGCHK_ENTRY 0x81
+#define PAL_CALLSYS_ENTRY 0x83
+#define PAL_IMB_ENTRY 0x86
+#define PAL_RDUNIQUE_ENTRY 0x9E
+#define PAL_WRUNIQUE_ENTRY 0x9F
+#define PAL_GENTRAP_ENTRY 0xAA
+
+#if defined(KDEBUG)
+#define PAL_DBGSTOP_ENTRY 0xAD
+/* #define NUM_UNPRIV_CALL_PALS 10 */
+#else
+/* #define NUM_UNPRIV_CALL_PALS 9 */
+#endif /* KDEBUG */
+
+/*
+** OSF/1 Privileged CALL_PAL Entry Offsets:
+**
+** Entry Name Offset (Hex)
+**
+** halt 0000
+** cflush 0001
+** draina 0002
+** cserve 0009
+** swppal 000A
+** rdmces 0010
+** wrmces 0011
+** wrfen 002B
+** wrvptptr 002D
+** swpctx 0030
+** wrval 0031
+** rdval 0032
+** tbi 0033
+** wrent 0034
+** swpipl 0035
+** rdps 0036
+** wrkgp 0037
+** wrusp 0038
+** rdusp 003A
+** whami 003C
+** retsys 003D
+** rti 003F
+*/
+
+#define PAL_HALT_ENTRY 0x0000
+#define PAL_CFLUSH_ENTRY 0x0001
+#define PAL_DRAINA_ENTRY 0x0002
+#define PAL_CSERVE_ENTRY 0x0009
+#define PAL_SWPPAL_ENTRY 0x000A
+#define PAL_WRIPIR_ENTRY 0x000D
+#define PAL_RDMCES_ENTRY 0x0010
+#define PAL_WRMCES_ENTRY 0x0011
+#define PAL_WRFEN_ENTRY 0x002B
+#define PAL_WRVPTPTR_ENTRY 0x002D
+#define PAL_SWPCTX_ENTRY 0x0030
+#define PAL_WRVAL_ENTRY 0x0031
+#define PAL_RDVAL_ENTRY 0x0032
+#define PAL_TBI_ENTRY 0x0033
+#define PAL_WRENT_ENTRY 0x0034
+#define PAL_SWPIPL_ENTRY 0x0035
+#define PAL_RDPS_ENTRY 0x0036
+#define PAL_WRKGP_ENTRY 0x0037
+#define PAL_WRUSP_ENTRY 0x0038
+#define PAL_RDUSP_ENTRY 0x003A
+#define PAL_WHAMI_ENTRY 0x003C
+#define PAL_RETSYS_ENTRY 0x003D
+#define PAL_RTI_ENTRY 0x003F
+
+#define NUM_PRIV_CALL_PALS 23
+
+#endif
+
diff --git a/system/alpha/h/rpb.h b/system/alpha/h/rpb.h
new file mode 100644
index 000000000..1adaf82e7
--- /dev/null
+++ b/system/alpha/h/rpb.h
@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 1990 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University.
+ * All rights reserved.
+ *
+ * Author: Keith Bostic, Chris G. Demetriou
+ *
+ * Permission to use, copy, modify and distribute this software and
+ * its documentation is hereby granted, provided that both the copyright
+ * notice and this permission notice appear in all copies of the
+ * software, derivative works or modified versions, and any portions
+ * thereof, and that both notices appear in supporting documentation.
+ *
+ * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
+ * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
+ * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
+ *
+ * Carnegie Mellon requests users of this software to return to
+ *
+ * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
+ * School of Computer Science
+ * Carnegie Mellon University
+ * Pittsburgh PA 15213-3890
+ *
+ * any improvements or extensions that they make and grant Carnegie the
+ * rights to redistribute these changes.
+ */
+
+/*
+ * Defines for the architected startup addresses.
+ */
+#define HWRPB_ADDR 0x10000000 /* 256 MB */
+#define BOOT_ADDR 0x20000000 /* 512 MB */
+#define PGTBL_ADDR 0x40000000 /* 1 GB */
+
+/*
+ * Values for the "haltcode" field in the per-cpu portion of the HWRPB
+ *
+ * Bit defines for the "sysvar" field in the HWRPB.
+ * Each platform has different values for SYSBOARD and IOBOARD bits.
+ */
+#define HALT_PWRUP 0 /* power up */
+#define HALT_OPR 1 /* operator issued halt cmd */
+#define HALT_KSTK 2 /* kernel stack not valid */
+#define HALT_SCBB 3 /* invalid SCBB */
+#define HALT_PTBR 4 /* invalid PTBR */
+#define HALT_EXE 5 /* kernel executed halt instruction */
+#define HALT_DBLE 6 /* double error abort */
+
+/*
+ * Bit defines for the "state" field in the per-cpu portion of the HWRPB
+ */
+#define STATE_BIP 0x00000001 /* bootstrap in progress */
+#define STATE_RC 0x00000002 /* restart capable */
+#define STATE_PA 0x00000004 /* processor available to OS */
+#define STATE_PP 0x00000008 /* processor present */
+#define STATE_OH 0x00000010 /* operator halted */
+#define STATE_CV 0x00000020 /* context valid */
+#define STATE_PV 0x00000040 /* PALcode valid */
+#define STATE_PMV 0x00000080 /* PALcode memory valid */
+#define STATE_PL 0x00000100 /* PALcode loaded */
+#define STATE_HALT_MASK 0x00ff0000 /* Mask for Halt Requested field */
+#define STATE_DEFAULT 0x00000000 /* Default (no specific action) */
+#define STATE_SVRS_TERM 0x00010000 /* SAVE_TERM/RESTORE_TERM Exit */
+#define STATE_COLD_BOOT 0x00020000 /* Cold Bootstrap Requested */
+#define STATE_WARM_BOOT 0x00030000 /* Warm Bootstrap Requested */
+#define STATE_HALT 0x00040000 /* Remain halted (no restart) */
+
+
+#define SV_PF_RSVD 0x00000000 /* RESERVED */
+#define SV_RESERVED 0x00000000 /* All STS bits; 0 for back compat */
+#define SV_MPCAP 0x00000001 /* MP capable */
+#define SV_PF_UNITED 0x00000020 /* United */
+#define SV_PF_SEPARATE 0x00000040 /* Separate */
+#define SV_PF_FULLBB 0x00000060 /* Full battery backup */
+#define SV_POWERFAIL 0x000000e0 /* Powerfail implementation */
+#define SV_PF_RESTART 0x00000100 /* Powerfail restart */
+
+#define SV_GRAPHICS 0x00000200 /* Embedded graphics processor */
+
+#define SV_STS_MASK 0x0000fc00 /* STS bits - system and I/O board */
+#define SV_SANDPIPER 0x00000400 /* others define system platforms */
+#define SV_FLAMINGO 0x00000800 /* STS BIT SETTINGS */
+#define SV_HOTPINK 0x00000c00 /* STS BIT SETTINGS */
+#define SV_FLAMINGOPLUS 0x00001000 /* STS BIT SETTINGS */
+#define SV_ULTRA 0x00001400 /* STS BIT SETTINGS */
+#define SV_SANDPLUS 0x00001800 /* STS BIT SETTINGS */
+#define SV_SANDPIPER45 0x00001c00 /* STS BIT SETTINGS */
+#define SV_FLAMINGO45 0x00002000 /* STS BIT SETTINGS */
+
+#define SV_SABLE 0x00000400 /* STS BIT SETTINGS */
+
+#define SV_KN20AA 0x00000400 /* STS BIT SETTINGS */
+
+/*
+ * Values for the "console type" field in the CTB portion of the HWRPB
+ */
+#define CONS_NONE 0 /* no console present */
+#define CONS_SRVC 1 /* console is service processor */
+#define CONS_DZ 2 /* console is dz/dl VT device */
+#define CONS_GRPH 3 /* cons is gfx dev w/ dz/dl keybd*/
+#define CONS_REM 4 /* cons is remote, protocal enet/MOP */
+
+/*
+ * PALcode variants that we're interested in.
+ * Used as indices into the "palrev_avail" array in the per-cpu portion
+ * of the HWRPB.
+ */
+#define PALvar_reserved 0
+#define PALvar_OpenVMS 1
+#define PALvar_OSF1 2
+
+/*
+ * The Alpha restart parameter block, which is a page or 2 in low memory
+ */
+struct rpb {
+ struct rpb *rpb_selfref; /* 000: physical self-reference */
+ long rpb_string; /* 008: contains string "HWRPB" */
+ long rpb_vers; /* 010: HWRPB version number */
+ ulong rpb_size; /* 018: bytes in RPB perCPU CTB CRB MEMDSC */
+ ulong rpb_cpuid; /* 020: primary cpu id */
+ ulong rpb_pagesize; /* 028: page size in bytes */
+ ulong rpb_addrbits; /* 030: number of phys addr bits */
+ ulong rpb_maxasn; /* 038: max valid ASN */
+ char rpb_ssn[16]; /* 040: system serial num: 10 ascii chars */
+ ulong grpb_systype; /* 050: system type */
+ long rpb_sysvar; /* 058: system variation */
+ long rpb_sysrev; /* 060: system revision */
+ ulong rpb_clock; /* 068: scaled interval clock intr freq */
+ ulong rpb_counter; /* 070: cycle counter frequency */
+ ulong rpb_vptb; /* 078: virtual page table base */
+ long rpb_res1; /* 080: reserved */
+ ulong rpb_trans_off; /* 088: offset to translation buffer hint */
+ ulong rpb_numprocs; /* 090: number of processor slots */
+ ulong rpb_slotsize; /* 098: per-cpu slot size */
+ ulong rpb_percpu_off; /* 0A0: offset to per_cpu slots */
+ ulong rpb_num_ctb; /* 0A8: number of CTBs */
+ ulong rpb_ctb_size; /* 0B0: bytes in largest CTB */
+ ulong rpb_ctb_off; /* 0B8: offset to CTB (cons term block) */
+ ulong rpb_crb_off; /* 0C0: offset to CRB (cons routine block) */
+ ulong rpb_mdt_off; /* 0C8: offset to memory descriptor table */
+ ulong rpb_config_off; /* 0D0: offset to config data block */
+ ulong rpb_fru_off; /* 0D8: offset to FRU table */
+ void (*rpb_saveterm)(); /* 0E0: virt addr of save term routine */
+ long rpb_saveterm_pv; /* 0E8: proc value for save term routine */
+ void (*rpb_rstrterm)(); /* 0F0: virt addr of restore term routine */
+ long rpb_rstrterm_pv; /* 0F8: proc value for restore term routine */
+ void (*rpb_restart)(); /* 100: virt addr of CPU restart routine */
+ long rpb_restart_pv; /* 108: proc value for CPU restart routine */
+ long rpb_software; /* 110: used to determine presence of kdebug */
+ long rpb_hardware; /* 118: reserved for hardware */
+ long rpb_checksum; /* 120: checksum of prior entries in rpb */
+ long rpb_rxrdy; /* 128: receive ready bitmask */
+ long rpb_txrdy; /* 130: transmit ready bitmask */
+ ulong rpb_dsr_off; /* 138: Dynamic System Recog. offset */
+};
+
+#define rpb_kdebug rpb_software
+
+#define OSF_HWRPB_ADDR ((vm_offset_t)(-1L << 23))
+
+/*
+ * This is the format for the boot/restart HWPCB. It must match the
+ * initial fields of the pcb structure as defined in pcb.h, but must
+ * additionally contain the appropriate amount of padding to line up
+ * with formats used by other palcode types.
+ */
+struct bootpcb {
+ long rpb_ksp; /* 000: kernel stack pointer */
+ long rpb_usp; /* 008: user stack pointer */
+ long rpb_ptbr; /* 010: page table base register */
+ int rpb_cc; /* 018: cycle counter */
+ int rpb_asn; /* 01C: address space number */
+ long rpb_proc_uniq; /* 020: proc/thread unique value */
+ long rpb_fen; /* 028: floating point enable */
+ long rpb_palscr[2]; /* 030: pal scratch area */
+ long rpb_pcbpad[8]; /* 040: padding for fixed size */
+};
+
+/*
+ * Inter-Console Communications Buffer
+ * Used for the primary processor to communcate with the console
+ * of secondary processors.
+ */
+struct iccb {
+ uint iccb_rxlen; /* receive length in bytes */
+ uint iccb_txlen; /* transmit length in bytes */
+ char iccb_rxbuf[80]; /* receive buffer */
+ char iccb_txbuf[80]; /* transmit buffer */
+};
+
+/*
+ * The per-cpu portion of the Alpha HWRPB.
+ * Note that the main portion of the HWRPB is of variable size,
+ * hence this must be a separate structure.
+ *
+ */
+struct rpb_percpu {
+ struct bootpcb rpb_pcb; /* 000: boot/restart HWPCB */
+ long rpb_state; /* 080: per-cpu state bits */
+ long rpb_palmem; /* 088: palcode memory length */
+ long rpb_palscratch; /* 090: palcode scratch length */
+ long rpb_palmem_addr; /* 098: phys addr of palcode mem space */
+ long rpb_palscratch_addr; /* 0A0: phys addr of palcode scratch space */
+ long rpb_palrev; /* 0A8: PALcode rev required */
+ long rpb_proctype; /* 0B0: processor type */
+ long rpb_procvar; /* 0B8: processor variation */
+ long rpb_procrev; /* 0C0: processor revision */
+ char rpb_procsn[16]; /* 0C8: proc serial num: 10 ascii chars */
+ long rpb_logout; /* 0D8: phys addr of logout area */
+ long rpb_logout_len; /* 0E0: length in bytes of logout area */
+ long rpb_haltpb; /* 0E8: halt pcb base */
+ long rpb_haltpc; /* 0F0: halt pc */
+ long rpb_haltps; /* 0F8: halt ps */
+ long rpb_haltal; /* 100: halt arg list (R25) */
+ long rpb_haltra; /* 108: halt return address (R26) */
+ long rpb_haltpv; /* 110: halt procedure value (R27) */
+ long rpb_haltcode; /* 118: reason for halt */
+ long rpb_software; /* 120: for software */
+ struct iccb rpb_iccb; /* 128: inter-console communications buffer */
+ long rpb_palrev_avail[16]; /* 1D0: PALcode revs available */
+ long rpb_pcrsvd[6]; /* 250: reserved for arch use */
+/* the dump stack grows from the end of the rpb page not to reach here */
+};
+
+/* The firmware revision is in the (unused) first entry of palrevs available */
+#define rpb_firmrev rpb_palrev_avail[0]
+
+/*
+ * The memory cluster descriptor.
+ */
+struct rpb_cluster {
+ long rpb_pfn; /* 000: starting PFN of this cluster */
+ long rpb_pfncount; /* 008: count of PFNs in this cluster */
+ long rpb_pfntested; /* 010: count of tested PFNs in cluster */
+ long rpb_va; /* 018: va of bitmap */
+ long rpb_pa; /* 020: pa of bitmap */
+ long rpb_checksum; /* 028: checksum of bitmap */
+ long rpb_usage; /* 030: usage of cluster */
+};
+#define CLUSTER_USAGE_OS ((long)0)
+#define CLUSTER_USAGE_PAL ((long)1)
+#define CLUSTER_USAGE_NVRAM ((long)2)
+
+/*
+ * The "memory descriptor table" portion of the HWRPB.
+ * Note that the main portion of the HWRPB is of variable size and there is a
+ * variable number of per-cpu slots, hence this must be a separate structure.
+ * Also note that the memory descriptor table contains a fixed portion plus
+ * a variable number of "memory cluster descriptors" (one for each "cluster"
+ * of memory).
+ */
+struct rpb_mdt {
+ long rpb_checksum; /* 000: checksum of entire mem desc table */
+ long rpb_impaddr; /* 008: PA of implementation dep info */
+ long rpb_numcl; /* 010: number of clusters */
+ struct rpb_cluster rpb_cluster[1]; /* first instance of a cluster */
+};
+
+/*
+ * The "Console Terminal Block" portion of the HWRPB, for serial line
+ * UART console device.
+ */
+struct ctb_tt {
+
+ long ctb_type; /* 0: always 4 */
+ long ctb_unit; /* 8: */
+ long ctb_reserved; /* 16: */
+ long ctb_len; /* 24: bytes of info */
+ long ctb_ipl; /* 32: console ipl level */
+ long ctb_tintr_vec; /* 40: transmit vec (0x800) */
+ long ctb_rintr_vec; /* 48: receive vec (0x800) */
+#define CTB_GRAPHICS 3 /* graphics device */
+#define CTB_NETWORK 0xC0 /* network device */
+#define CTB_PRINTERPORT 2 /* printer port on the SCC */
+ long ctb_term_type; /* 56: terminal type */
+ long ctb_keybd_type; /* 64: keyboard nationality */
+ long ctb_keybd_trans; /* 72: trans. table addr */
+ long ctb_keybd_map; /* 80: map table addr */
+ long ctb_keybd_state; /* 88: keyboard flags */
+ long ctb_keybd_last; /* 96: last key entered */
+ long ctb_font_us; /* 104: US font table addr */
+ long ctb_font_mcs; /* 112: MCS font table addr */
+ long ctb_font_width; /* 120: font width, height */
+ long ctb_font_height; /* 128: in pixels */
+ long ctb_mon_width; /* 136: monitor width, height */
+ long ctb_mon_height; /* 144: in pixels */
+ long ctb_dpi; /* 152: monitor dots per inch */
+ long ctb_planes; /* 160: # of planes */
+ long ctb_cur_width; /* 168: cursor width, height */
+ long ctb_cur_height; /* 176: in pixels */
+ long ctb_head_cnt; /* 184: # of heads */
+ long ctb_opwindow; /* 192: opwindow on screen */
+ long ctb_head_offset; /* 200: offset to head info */
+ long ctb_putchar; /* 208: output char to TURBO */
+ long ctb_io_state; /* 216: I/O flags */
+ long ctb_listen_state; /* 224: listener flags */
+ long ctb_xaddr; /* 232: extended info addr */
+ long ctb_turboslot; /* 248: TURBOchannel slot # */
+ long ctb_server_off; /* 256: offset to server info */
+ long ctb_line_off; /* 264: line parameter offset */
+ char ctb_csd; /* 272: console specific data */
+};
+
+/*
+ * The "Console Terminal Block" portion of the HWRPB.
+ */
+struct rpb_ctb {
+ long rpb_type; /* 000: console type */
+ long rpb_unit; /* 008: console unit */
+ long rpb_resv; /* 010: reserved */
+ long rpb_length; /* 018: byte length of device dep portion */
+ long rpb_first; /* 000: first field of device dep portion */
+};
+
+/*
+ * The physical/virtual map for the console routine block.
+ */
+struct rpb_map {
+ long rpb_virt; /* virtual address for map entry */
+ long rpb_phys; /* phys address for map entry */
+ long rpb_pgcount; /* page count for map entry */
+};
+
+/*
+ * The "Console Routine Block" portion of the HWRPB.
+ * Note: the "offsets" are all relative to the start of the HWRPB (HWRPB_ADDR).
+ */
+struct rpb_crb {
+ long rpb_va_disp; /* va of call-back dispatch rtn */
+ long rpb_pa_disp; /* pa of call-back dispatch rtn */
+ long rpb_va_fixup; /* va of call-back fixup rtn */
+ long rpb_pa_fixup; /* pa of call-back fixup rtn */
+ long rpb_num; /* number of entries in phys/virt map */
+ long rpb_mapped_pages; /* Number of pages to be mapped */
+ struct rpb_map rpb_map[1]; /* first instance of a map entry */
+};
+
+/*
+ * These macros define where within the HWRPB the CTB and CRB are located.
+ */
+#define CTB_SETUP \
+ ((struct rpb_ctb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_ctb_off)))
+
+#define CRB_SETUP \
+ ((struct rpb_crb *) ((long)hwrpb_addr + (long)(hwrpb_addr->rpb_crb_off)))
+
+/*
+ * The "Dynamic System Recognition" portion of the HWRPB.
+ * It is used to obtain the platform specific data need to allow
+ * the platform define the platform name, the platform SMM and LURT
+ * data for software licensing
+ */
+struct rpb_dsr {
+ long rpb_smm; /* SMM nubber used by LMF */
+ ulong rpb_lurt_off; /* offset to LURT table */
+ ulong rpb_sysname_off; /* offset to sysname char count */
+ int lurt[10]; /* XXM has one LURT entry */
+};
diff --git a/system/alpha/h/tlaser.h b/system/alpha/h/tlaser.h
new file mode 100644
index 000000000..283d61be3
--- /dev/null
+++ b/system/alpha/h/tlaser.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 1990 Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define tlsb_tlber 0x40
+#define tlsb_tldev 0x00
+#define tlsb_tlesr0 0x680
+#define tlsb_tlesr1 0x6C0
+#define tlsb_tlesr2 0x700
+#define tlsb_tlesr3 0x740
diff --git a/system/alpha/palcode/Makefile b/system/alpha/palcode/Makefile
new file mode 100644
index 000000000..2f1eded33
--- /dev/null
+++ b/system/alpha/palcode/Makefile
@@ -0,0 +1,92 @@
+# Copyright (c) 2003, 2004
+# The Regents of The University of Michigan
+# All Rights Reserved
+#
+# This code is part of the M5 simulator.
+#
+# Permission is granted to use, copy, create derivative works and
+# redistribute this software and such derivative works for any purpose,
+# so long as the copyright notice above, this grant of permission, and
+# the disclaimer below appear in all copies made; and so long as the
+# name of The University of Michigan is not used in any advertising or
+# publicity pertaining to the use or distribution of this software
+# without specific, written prior authorization.
+#
+# THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE
+# UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT
+# WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF
+# THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,
+# INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL
+# DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION
+# WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+#
+# Authors: Nathan L. Binkert
+# Ali G. Saidi
+
+# Makefile for palcode
+# Works on alpha-linux and builds elf executable
+
+### If we are not compiling on an alpha, we must use cross tools ###
+ifneq ($(shell uname -m), alpha)
+CROSS_COMPILE?=alpha-unknown-linux-gnu-
+endif
+CC=$(CROSS_COMPILE)gcc
+AS=$(CROSS_COMPILE)as
+LD=$(CROSS_COMPILE)ld
+
+CFLAGS=-I . -I ../h -nostdinc -nostdinc++ -Wa,-m21164
+LDFLAGS=-Ttext 0x4000
+
+TLOBJS = osfpal.o platform_tlaser.o
+TLOBJS_COPY = osfpal_cache_copy.o platform_tlaser.o
+TLOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_tlaser.o
+TSOBJS = osfpal.o platform_tsunami.o
+TSBOBJS = osfpal.o platform_bigtsunami.o
+TSOBJS_COPY = osfpal_cache_copy.o platform_tsunami.o
+TSOBJS_COPY_UNALIGNED = osfpal_cache_copy_unaligned.o platform_bigtsunami.o
+
+all: tlaser tsunami tsunami_b64
+
+all_copy: tlaser tlaser_copy tsunami tsunami_b64 tsunami_copy
+
+osfpal.o: osfpal.S
+ $(CC) $(CFLAGS) -o $@ -c $<
+
+osfpal_cache_copy.o: osfpal.S
+ $(CC) $(CFLAGS) -DCACHE_COPY -o $@ -c $<
+
+osfpal_cache_copy_unaligned.o: osfpal.S
+ $(CC) $(CFLAGS) -DCACHE_COPY -DCACHE_COPY_UNALIGNED -o $@ -c $<
+
+platform_tlaser.o: platform.S
+ $(CC) $(CFLAGS) -DTLASER -o $@ -c $<
+
+platform_tsunami.o: platform.S
+ $(CC) $(CFLAGS) -DTSUNAMI -o $@ -c $<
+
+platform_bigtsunami.o: platform.S
+ $(CC) $(CFLAGS) -DBIG_TSUNAMI -o $@ -c $<
+
+tlaser: $(TLOBJS)
+ $(LD) $(LDFLAGS) -o tl_osfpal $(TLOBJS)
+
+tlaser_copy: $(TLOBJS_COPY) $(TLOBJS_COPY_UNALIGNED)
+ $(LD) $(LDFLAGS) -o tl_osfpal_cache $(TLOBJS_COPY)
+ $(LD) $(LDFLAGS) -o tl_osfpal_unalign $(TLOBJS_COPY_UNALIGNED)
+
+tsunami: $(TSOBJS)
+ $(LD) $(LDFLAGS) -o ts_osfpal $(TSOBJS)
+
+tsunami_b64: $(TSBOBJS)
+ $(LD) $(LDFLAGS) -o tsb_osfpal $(TSBOBJS)
+
+tsunami_copy: $(TSOBJS_COPY) $(TSOBJS_COPY_UNALIGNED)
+ $(LD) $(LDFLAGS) -o ts_osfpal_cache $(TSOBJS_COPY)
+ $(LD) $(LDFLAGS) -o ts_osfpal_unalign $(TSOBJS_COPY_UNALIGNED)
+
+clean:
+ rm -f *.o tl_osfpal tl_osfpal_cache tl_osfpal_unalign ts_osfpal \
+ ts_osfpal_cache ts_osfpal_unalign tsb_osfpal
diff --git a/system/alpha/palcode/osfpal.S b/system/alpha/palcode/osfpal.S
new file mode 100644
index 000000000..3ec4d4011
--- /dev/null
+++ b/system/alpha/palcode/osfpal.S
@@ -0,0 +1,4202 @@
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * Copyright (c) 1992-1995 Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali G. Saidi
+ * Nathan L. Binkert
+ */
+
+// modified to use the Hudson style "impure.h" instead of ev5_impure.sdl
+// since we don't have a mechanism to expand the data structures.... pb Nov/95
+#include "ev5_defs.h"
+#include "ev5_impure.h"
+#include "ev5_alpha_defs.h"
+#include "ev5_paldef.h"
+#include "ev5_osfalpha_defs.h"
+#include "fromHudsonMacros.h"
+#include "fromHudsonOsf.h"
+#include "dc21164FromGasSources.h"
+
+#define DEBUGSTORE(c) nop
+
+#define DEBUG_EXC_ADDR()\
+ bsr r25, put_exc_addr; \
+ DEBUGSTORE(13) ; \
+ DEBUGSTORE(10)
+
+// This is the fix for the user-mode super page references causing the
+// machine to crash.
+#define hw_rei_spe hw_rei
+
+#define vmaj 1
+#define vmin 18
+#define vms_pal 1
+#define osf_pal 2
+#define pal_type osf_pal
+#define osfpal_version_l ((pal_type<<16) | (vmaj<<8) | (vmin<<0))
+
+
+///////////////////////////
+// PALtemp register usage
+///////////////////////////
+
+// The EV5 Ibox holds 24 PALtemp registers. This maps the OSF PAL usage
+// for these PALtemps:
+//
+// pt0 local scratch
+// pt1 local scratch
+// pt2 entUna pt_entUna
+// pt3 CPU specific impure area pointer pt_impure
+// pt4 memory management temp
+// pt5 memory management temp
+// pt6 memory management temp
+// pt7 entIF pt_entIF
+// pt8 intmask pt_intmask
+// pt9 entSys pt_entSys
+// pt10
+// pt11 entInt pt_entInt
+// pt12 entArith pt_entArith
+// pt13 reserved for system specific PAL
+// pt14 reserved for system specific PAL
+// pt15 reserved for system specific PAL
+// pt16 MISC: scratch ! WHAMI<7:0> ! 0 0 0 MCES<4:0> pt_misc, pt_whami,
+// pt_mces
+// pt17 sysval pt_sysval
+// pt18 usp pt_usp
+// pt19 ksp pt_ksp
+// pt20 PTBR pt_ptbr
+// pt21 entMM pt_entMM
+// pt22 kgp pt_kgp
+// pt23 PCBB pt_pcbb
+//
+//
+
+
+/////////////////////////////
+// PALshadow register usage
+/////////////////////////////
+
+//
+// EV5 shadows R8-R14 and R25 when in PALmode and ICSR<shadow_enable> = 1.
+// This maps the OSF PAL usage of R8 - R14 and R25:
+//
+// r8 ITBmiss/DTBmiss scratch
+// r9 ITBmiss/DTBmiss scratch
+// r10 ITBmiss/DTBmiss scratch
+// r11 PS
+// r12 local scratch
+// r13 local scratch
+// r14 local scratch
+// r25 local scratch
+//
+
+
+
+// .sbttl "PALcode configuration options"
+
+// There are a number of options that may be assembled into this version of
+// PALcode. They should be adjusted in a prefix assembly file (i.e. do not edit
+// the following). The options that can be adjusted cause the resultant PALcode
+// to reflect the desired target system.
+
+// multiprocessor support can be enabled for a max of n processors by
+// setting the following to the number of processors on the system.
+// Note that this is really the max cpuid.
+
+#define max_cpuid 1
+#ifndef max_cpuid
+#define max_cpuid 8
+#endif
+
+#define osf_svmin 1
+#define osfpal_version_h ((max_cpuid<<16) | (osf_svmin<<0))
+
+//
+// RESET - Reset Trap Entry Point
+//
+// RESET - offset 0000
+// Entry:
+// Vectored into via hardware trap on reset, or branched to
+// on swppal.
+//
+// r0 = whami
+// r1 = pal_base
+// r2 = base of scratch area
+// r3 = halt code
+//
+//
+// Function:
+//
+//
+
+ .text 0
+ . = 0x0000
+ .globl _start
+ .globl Pal_Base
+_start:
+Pal_Base:
+ HDW_VECTOR(PAL_RESET_ENTRY)
+Trap_Reset:
+ nop
+ /*
+ * store into r1
+ */
+ br r1,sys_reset
+
+ // Specify PAL version info as a constant
+ // at a known location (reset + 8).
+
+ .long osfpal_version_l // <pal_type@16> ! <vmaj@8> ! <vmin@0>
+ .long osfpal_version_h // <max_cpuid@16> ! <osf_svmin@0>
+ .long 0
+ .long 0
+pal_impure_start:
+ .quad 0
+pal_debug_ptr:
+ .quad 0 // reserved for debug pointer ; 20
+
+
+//
+// IACCVIO - Istream Access Violation Trap Entry Point
+//
+// IACCVIO - offset 0080
+// Entry:
+// Vectored into via hardware trap on Istream access violation or sign check error on PC.
+//
+// Function:
+// Build stack frame
+// a0 <- Faulting VA
+// a1 <- MMCSR (1 for ACV)
+// a2 <- -1 (for ifetch fault)
+// vector via entMM
+//
+
+ HDW_VECTOR(PAL_IACCVIO_ENTRY)
+Trap_Iaccvio:
+ DEBUGSTORE(0x42)
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ bis r11, r31, r12 // Save PS
+ bge r25, TRAP_IACCVIO_10_ // no stack swap needed if cm=kern
+
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r12 // Set new PS
+ mfpr r30, pt_ksp
+
+TRAP_IACCVIO_10_:
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+ mfpr r14, exc_addr // get pc
+
+ stq r16, osfsf_a0(sp) // save regs
+ bic r14, 3, r16 // pass pc/va as a0
+
+ stq r17, osfsf_a1(sp) // a1
+ or r31, mmcsr_c_acv, r17 // pass mm_csr as a1
+
+ stq r18, osfsf_a2(sp) // a2
+ mfpr r13, pt_entmm // get entry point
+
+ stq r11, osfsf_ps(sp) // save old ps
+ bis r12, r31, r11 // update ps
+
+ stq r16, osfsf_pc(sp) // save pc
+ stq r29, osfsf_gp(sp) // save gp
+
+ mtpr r13, exc_addr // load exc_addr with entMM
+ // 1 cycle to hw_rei
+ mfpr r29, pt_kgp // get the kgp
+
+ subq r31, 1, r18 // pass flag of istream, as a2
+ hw_rei_spe
+
+
+//
+// INTERRUPT - Interrupt Trap Entry Point
+//
+// INTERRUPT - offset 0100
+// Entry:
+// Vectored into via trap on hardware interrupt
+//
+// Function:
+// check for halt interrupt
+// check for passive release (current ipl geq requestor)
+// if necessary, switch to kernel mode push stack frame,
+// update ps (including current mode and ipl copies), sp, and gp
+// pass the interrupt info to the system module
+//
+//
+ HDW_VECTOR(PAL_INTERRUPT_ENTRY)
+Trap_Interrupt:
+ mfpr r13, ev5__intid // Fetch level of interruptor
+ mfpr r25, ev5__isr // Fetch interrupt summary register
+
+ srl r25, isr_v_hlt, r9 // Get HLT bit
+ mfpr r14, ev5__ipl
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kern
+ blbs r9, sys_halt_interrupt // halt_interrupt if HLT bit set
+
+ cmple r13, r14, r8 // R8 = 1 if intid .less than or eql. ipl
+ bne r8, sys_passive_release // Passive release is current rupt is lt or eq ipl
+
+ and r11, osfps_m_mode, r10 // get mode bit
+ beq r10, TRAP_INTERRUPT_10_ // Skip stack swap in kernel
+
+ mtpr r30, pt_usp // save user stack
+ mfpr r30, pt_ksp // get kern stack
+
+TRAP_INTERRUPT_10_:
+ lda sp, (0-osfsf_c_size)(sp)// allocate stack space
+ mfpr r14, exc_addr // get pc
+
+ stq r11, osfsf_ps(sp) // save ps
+ stq r14, osfsf_pc(sp) // save pc
+
+ stq r29, osfsf_gp(sp) // push gp
+ stq r16, osfsf_a0(sp) // a0
+
+// pvc_violate 354 // ps is cleared anyway, if store to stack faults.
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+ stq r17, osfsf_a1(sp) // a1
+
+ stq r18, osfsf_a2(sp) // a2
+ subq r13, 0x11, r12 // Start to translate from EV5IPL->OSFIPL
+
+ srl r12, 1, r8 // 1d, 1e: ipl 6. 1f: ipl 7.
+ subq r13, 0x1d, r9 // Check for 1d, 1e, 1f
+
+ cmovge r9, r8, r12 // if .ge. 1d, then take shifted value
+ bis r12, r31, r11 // set new ps
+
+ mfpr r12, pt_intmask
+ and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already)
+
+ /*
+ * Lance had space problems. We don't.
+ */
+ extbl r12, r14, r14 // Translate new OSFIPL->EV5IPL
+ mfpr r29, pt_kgp // update gp
+ mtpr r14, ev5__ipl // load the new IPL into Ibox
+ br r31, sys_interrupt // Go handle interrupt
+
+
+
+//
+// ITBMISS - Istream TBmiss Trap Entry Point
+//
+// ITBMISS - offset 0180
+// Entry:
+// Vectored into via hardware trap on Istream translation buffer miss.
+//
+// Function:
+// Do a virtual fetch of the PTE, and fill the ITB if the PTE is valid.
+// Can trap into DTBMISS_DOUBLE.
+// This routine can use the PALshadow registers r8, r9, and r10
+//
+//
+
+ HDW_VECTOR(PAL_ITB_MISS_ENTRY)
+Trap_Itbmiss:
+ // Real MM mapping
+ nop
+ mfpr r8, ev5__ifault_va_form // Get virtual address of PTE.
+
+ nop
+ mfpr r10, exc_addr // Get PC of faulting instruction in case of DTBmiss.
+
+pal_itb_ldq:
+ ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss
+ mtpr r10, exc_addr // Restore exc_address if there was a trap.
+
+ mfpr r31, ev5__va // Unlock VA in case there was a double miss
+ nop
+
+ and r8, osfpte_m_foe, r25 // Look for FOE set.
+ blbc r8, invalid_ipte_handler // PTE not valid.
+
+ nop
+ bne r25, foe_ipte_handler // FOE is set
+
+ nop
+ mtpr r8, ev5__itb_pte // Ibox remembers the VA, load the PTE into the ITB.
+
+ hw_rei_stall //
+
+
+//
+// DTBMISS_SINGLE - Dstream Single TBmiss Trap Entry Point
+//
+// DTBMISS_SINGLE - offset 0200
+// Entry:
+// Vectored into via hardware trap on Dstream single translation
+// buffer miss.
+//
+// Function:
+// Do a virtual fetch of the PTE, and fill the DTB if the PTE is valid.
+// Can trap into DTBMISS_DOUBLE.
+// This routine can use the PALshadow registers r8, r9, and r10
+//
+
+ HDW_VECTOR(PAL_DTB_MISS_ENTRY)
+Trap_Dtbmiss_Single:
+ mfpr r8, ev5__va_form // Get virtual address of PTE - 1 cycle delay. E0.
+ mfpr r10, exc_addr // Get PC of faulting instruction in case of error. E1.
+
+// DEBUGSTORE(0x45)
+// DEBUG_EXC_ADDR()
+ // Real MM mapping
+ mfpr r9, ev5__mm_stat // Get read/write bit. E0.
+ mtpr r10, pt6 // Stash exc_addr away
+
+pal_dtb_ldq:
+ ld_vpte r8, 0(r8) // Get PTE, traps to DTBMISS_DOUBLE in case of TBmiss
+ nop // Pad MF VA
+
+ mfpr r10, ev5__va // Get original faulting VA for TB load. E0.
+ nop
+
+ mtpr r8, ev5__dtb_pte // Write DTB PTE part. E0.
+ blbc r8, invalid_dpte_handler // Handle invalid PTE
+
+ mtpr r10, ev5__dtb_tag // Write DTB TAG part, completes DTB load. No virt ref for 3 cycles.
+ mfpr r10, pt6
+
+ // Following 2 instructions take 2 cycles
+ mtpr r10, exc_addr // Return linkage in case we trapped. E1.
+ mfpr r31, pt0 // Pad the write to dtb_tag
+
+ hw_rei // Done, return
+
+
+//
+// DTBMISS_DOUBLE - Dstream Double TBmiss Trap Entry Point
+//
+//
+// DTBMISS_DOUBLE - offset 0280
+// Entry:
+// Vectored into via hardware trap on Double TBmiss from single
+// miss flows.
+//
+// r8 - faulting VA
+// r9 - original MMstat
+// r10 - original exc_addr (both itb,dtb miss)
+// pt6 - original exc_addr (dtb miss flow only)
+// VA IPR - locked with original faulting VA
+//
+// Function:
+// Get PTE, if valid load TB and return.
+// If not valid then take TNV/ACV exception.
+//
+// pt4 and pt5 are reserved for this flow.
+//
+//
+//
+
+ HDW_VECTOR(PAL_DOUBLE_MISS_ENTRY)
+Trap_Dtbmiss_double:
+ mtpr r8, pt4 // save r8 to do exc_addr check
+ mfpr r8, exc_addr
+ blbc r8, Trap_Dtbmiss_Single //if not in palmode, should be in the single routine, dummy!
+ mfpr r8, pt4 // restore r8
+ nop
+ mtpr r22, pt5 // Get some scratch space. E1.
+ // Due to virtual scheme, we can skip the first lookup and go
+ // right to fetch of level 2 PTE
+ sll r8, (64-((2*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA
+ mtpr r21, pt4 // Get some scratch space. E1.
+
+ srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8
+ mfpr r21, pt_ptbr // Get physical address of the page table.
+
+ nop
+ addq r21, r22, r21 // Index into page table for level 2 PTE.
+
+ sll r8, (64-((1*page_seg_size_bits)+page_offset_size_bits)), r22 // Clean off upper bits of VA
+ ldq_p r21, 0(r21) // Get level 2 PTE (addr<2:0> ignored)
+
+ srl r22, 61-page_seg_size_bits, r22 // Get Va<seg1>*8
+ blbc r21, double_pte_inv // Check for Invalid PTE.
+
+ srl r21, 32, r21 // extract PFN from PTE
+ sll r21, page_offset_size_bits, r21 // get PFN * 2^13 for add to <seg3>*8
+
+ addq r21, r22, r21 // Index into page table for level 3 PTE.
+ nop
+
+ ldq_p r21, 0(r21) // Get level 3 PTE (addr<2:0> ignored)
+ blbc r21, double_pte_inv // Check for invalid PTE.
+
+ mtpr r21, ev5__dtb_pte // Write the PTE. E0.
+ mfpr r22, pt5 // Restore scratch register
+
+ mtpr r8, ev5__dtb_tag // Write the TAG. E0. No virtual references in subsequent 3 cycles.
+ mfpr r21, pt4 // Restore scratch register
+
+ nop // Pad write to tag.
+ nop
+
+ nop // Pad write to tag.
+ nop
+
+ hw_rei
+
+
+
+//
+// UNALIGN -- Dstream unalign trap
+//
+// UNALIGN - offset 0300
+// Entry:
+// Vectored into via hardware trap on unaligned Dstream reference.
+//
+// Function:
+// Build stack frame
+// a0 <- Faulting VA
+// a1 <- Opcode
+// a2 <- src/dst register number
+// vector via entUna
+//
+
+ HDW_VECTOR(PAL_UNALIGN_ENTRY)
+Trap_Unalign:
+/* DEBUGSTORE(0x47)*/
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ mfpr r8, ev5__mm_stat // Get mmstat --ok to use r8, no tbmiss
+ mfpr r14, exc_addr // get pc
+
+ srl r8, mm_stat_v_ra, r13 // Shift Ra field to ls bits
+ blbs r14, pal_pal_bug_check // Bugcheck if unaligned in PAL
+
+ blbs r8, UNALIGN_NO_DISMISS // lsb only set on store or fetch_m
+ // not set, must be a load
+ and r13, 0x1F, r8 // isolate ra
+
+ cmpeq r8, 0x1F, r8 // check for r31/F31
+ bne r8, dfault_fetch_ldr31_err // if its a load to r31 or f31 -- dismiss the fault
+
+UNALIGN_NO_DISMISS:
+ bis r11, r31, r12 // Save PS
+ bge r25, UNALIGN_NO_DISMISS_10_ // no stack swap needed if cm=kern
+
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r12 // Set new PS
+ mfpr r30, pt_ksp
+
+UNALIGN_NO_DISMISS_10_:
+ mfpr r25, ev5__va // Unlock VA
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+
+ mtpr r25, pt0 // Stash VA
+ stq r18, osfsf_a2(sp) // a2
+
+ stq r11, osfsf_ps(sp) // save old ps
+ srl r13, mm_stat_v_opcode-mm_stat_v_ra, r25// Isolate opcode
+
+ stq r29, osfsf_gp(sp) // save gp
+ addq r14, 4, r14 // inc PC past the ld/st
+
+ stq r17, osfsf_a1(sp) // a1
+ and r25, mm_stat_m_opcode, r17// Clean opocde for a1
+
+ stq r16, osfsf_a0(sp) // save regs
+ mfpr r16, pt0 // a0 <- va/unlock
+
+ stq r14, osfsf_pc(sp) // save pc
+ mfpr r25, pt_entuna // get entry point
+
+
+ bis r12, r31, r11 // update ps
+ br r31, unalign_trap_cont
+
+
+//
+// DFAULT - Dstream Fault Trap Entry Point
+//
+// DFAULT - offset 0380
+// Entry:
+// Vectored into via hardware trap on dstream fault or sign check
+// error on DVA.
+//
+// Function:
+// Ignore faults on FETCH/FETCH_M
+// Check for DFAULT in PAL
+// Build stack frame
+// a0 <- Faulting VA
+// a1 <- MMCSR (1 for ACV, 2 for FOR, 4 for FOW)
+// a2 <- R/W
+// vector via entMM
+//
+//
+ HDW_VECTOR(PAL_D_FAULT_ENTRY)
+Trap_Dfault:
+// DEBUGSTORE(0x48)
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ mfpr r13, ev5__mm_stat // Get mmstat
+ mfpr r8, exc_addr // get pc, preserve r14
+
+ srl r13, mm_stat_v_opcode, r9 // Shift opcode field to ls bits
+ blbs r8, dfault_in_pal
+
+ bis r8, r31, r14 // move exc_addr to correct place
+ bis r11, r31, r12 // Save PS
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ and r9, mm_stat_m_opcode, r9 // Clean all but opcode
+
+ cmpeq r9, evx_opc_sync, r9 // Is the opcode fetch/fetchm?
+ bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault
+
+ //dismiss exception if load to r31/f31
+ blbs r13, dfault_no_dismiss // mm_stat<0> set on store or fetchm
+
+ // not a store or fetch, must be a load
+ srl r13, mm_stat_v_ra, r9 // Shift rnum to low bits
+
+ and r9, 0x1F, r9 // isolate rnum
+ nop
+
+ cmpeq r9, 0x1F, r9 // Is the rnum r31 or f31?
+ bne r9, dfault_fetch_ldr31_err // Yes, dismiss the fault
+
+dfault_no_dismiss:
+ and r13, 0xf, r13 // Clean extra bits in mm_stat
+ bge r25, dfault_trap_cont // no stack swap needed if cm=kern
+
+
+ mtpr r30, pt_usp // save user stack
+ bis r31, r31, r12 // Set new PS
+
+ mfpr r30, pt_ksp
+ br r31, dfault_trap_cont
+
+
+//
+// MCHK - Machine Check Trap Entry Point
+//
+// MCHK - offset 0400
+// Entry:
+// Vectored into via hardware trap on machine check.
+//
+// Function:
+//
+//
+
+ HDW_VECTOR(PAL_MCHK_ENTRY)
+Trap_Mchk:
+ DEBUGSTORE(0x49)
+ mtpr r31, ic_flush_ctl // Flush the Icache
+ br r31, sys_machine_check
+
+
+//
+// OPCDEC - Illegal Opcode Trap Entry Point
+//
+// OPCDEC - offset 0480
+// Entry:
+// Vectored into via hardware trap on illegal opcode.
+//
+// Build stack frame
+// a0 <- code
+// a1 <- unpred
+// a2 <- unpred
+// vector via entIF
+//
+//
+
+ HDW_VECTOR(PAL_OPCDEC_ENTRY)
+Trap_Opcdec:
+ DEBUGSTORE(0x4a)
+//simos DEBUG_EXC_ADDR()
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ mfpr r14, exc_addr // get pc
+ blbs r14, pal_pal_bug_check // check opcdec in palmode
+
+ bis r11, r31, r12 // Save PS
+ bge r25, TRAP_OPCDEC_10_ // no stack swap needed if cm=kern
+
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r12 // Set new PS
+ mfpr r30, pt_ksp
+
+TRAP_OPCDEC_10_:
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+ addq r14, 4, r14 // inc pc
+
+ stq r16, osfsf_a0(sp) // save regs
+ bis r31, osf_a0_opdec, r16 // set a0
+
+ stq r11, osfsf_ps(sp) // save old ps
+ mfpr r13, pt_entif // get entry point
+
+ stq r18, osfsf_a2(sp) // a2
+ stq r17, osfsf_a1(sp) // a1
+
+ stq r29, osfsf_gp(sp) // save gp
+ stq r14, osfsf_pc(sp) // save pc
+
+ bis r12, r31, r11 // update ps
+ mtpr r13, exc_addr // load exc_addr with entIF
+ // 1 cycle to hw_rei, E1
+
+ mfpr r29, pt_kgp // get the kgp, E1
+
+ hw_rei_spe // done, E1
+
+
+//
+// ARITH - Arithmetic Exception Trap Entry Point
+//
+// ARITH - offset 0500
+// Entry:
+// Vectored into via hardware trap on arithmetic excpetion.
+//
+// Function:
+// Build stack frame
+// a0 <- exc_sum
+// a1 <- exc_mask
+// a2 <- unpred
+// vector via entArith
+//
+//
+ HDW_VECTOR(PAL_ARITH_ENTRY)
+Trap_Arith:
+ DEBUGSTORE(0x4b)
+ and r11, osfps_m_mode, r12 // get mode bit
+ mfpr r31, ev5__va // unlock mbox
+
+ bis r11, r31, r25 // save ps
+ mfpr r14, exc_addr // get pc
+
+ nop
+ blbs r14, pal_pal_bug_check // arith trap from PAL
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ beq r12, TRAP_ARITH_10_ // if zero we are in kern now
+
+ bis r31, r31, r25 // set the new ps
+ mtpr r30, pt_usp // save user stack
+
+ nop
+ mfpr r30, pt_ksp // get kern stack
+
+TRAP_ARITH_10_: lda sp, 0-osfsf_c_size(sp) // allocate stack space
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ nop // Pad current mode write and stq
+ mfpr r13, ev5__exc_sum // get the exc_sum
+
+ mfpr r12, pt_entarith
+ stq r14, osfsf_pc(sp) // save pc
+
+ stq r17, osfsf_a1(sp)
+ mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle
+
+ stq r11, osfsf_ps(sp) // save ps
+ bis r25, r31, r11 // set new ps
+
+ stq r16, osfsf_a0(sp) // save regs
+ srl r13, exc_sum_v_swc, r16 // shift data to correct position
+
+ stq r18, osfsf_a2(sp)
+// pvc_violate 354 // ok, but make sure reads of exc_mask/sum are not in same trap shadow
+ mtpr r31, ev5__exc_sum // Unlock exc_sum and exc_mask
+
+ stq r29, osfsf_gp(sp)
+ mtpr r12, exc_addr // Set new PC - 1 bubble to hw_rei - E1
+
+ mfpr r29, pt_kgp // get the kern gp - E1
+ hw_rei_spe // done - E1
+
+
+//
+// FEN - Illegal Floating Point Operation Trap Entry Point
+//
+// FEN - offset 0580
+// Entry:
+// Vectored into via hardware trap on illegal FP op.
+//
+// Function:
+// Build stack frame
+// a0 <- code
+// a1 <- unpred
+// a2 <- unpred
+// vector via entIF
+//
+//
+
+ HDW_VECTOR(PAL_FEN_ENTRY)
+Trap_Fen:
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ mfpr r14, exc_addr // get pc
+ blbs r14, pal_pal_bug_check // check opcdec in palmode
+
+ mfpr r13, ev5__icsr
+ nop
+
+ bis r11, r31, r12 // Save PS
+ bge r25, TRAP_FEN_10_ // no stack swap needed if cm=kern
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r12 // Set new PS
+ mfpr r30, pt_ksp
+
+TRAP_FEN_10_:
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+ srl r13, icsr_v_fpe, r25 // Shift FP enable to bit 0
+
+
+ stq r16, osfsf_a0(sp) // save regs
+ mfpr r13, pt_entif // get entry point
+
+ stq r18, osfsf_a2(sp) // a2
+ stq r11, osfsf_ps(sp) // save old ps
+
+ stq r29, osfsf_gp(sp) // save gp
+ bis r12, r31, r11 // set new ps
+
+ stq r17, osfsf_a1(sp) // a1
+ blbs r25,fen_to_opcdec // If FP is enabled, this is really OPCDEC.
+
+ bis r31, osf_a0_fen, r16 // set a0
+ stq r14, osfsf_pc(sp) // save pc
+
+ mtpr r13, exc_addr // load exc_addr with entIF
+ // 1 cycle to hw_rei -E1
+
+ mfpr r29, pt_kgp // get the kgp -E1
+
+ hw_rei_spe // done -E1
+
+// FEN trap was taken, but the fault is really opcdec.
+ ALIGN_BRANCH
+fen_to_opcdec:
+ addq r14, 4, r14 // save PC+4
+ bis r31, osf_a0_opdec, r16 // set a0
+
+ stq r14, osfsf_pc(sp) // save pc
+ mtpr r13, exc_addr // load exc_addr with entIF
+ // 1 cycle to hw_rei
+
+ mfpr r29, pt_kgp // get the kgp
+ hw_rei_spe // done
+
+
+
+//////////////////////////////////////////////////////////////////////////////
+// Misc handlers - Start area for misc code.
+//////////////////////////////////////////////////////////////////////////////
+
+//
+// dfault_trap_cont
+// A dfault trap has been taken. The sp has been updated if necessary.
+// Push a stack frame a vector via entMM.
+//
+// Current state:
+// r12 - new PS
+// r13 - MMstat
+// VA - locked
+//
+//
+ ALIGN_BLOCK
+dfault_trap_cont:
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+ mfpr r25, ev5__va // Fetch VA/unlock
+
+ stq r18, osfsf_a2(sp) // a2
+ and r13, 1, r18 // Clean r/w bit for a2
+
+ stq r16, osfsf_a0(sp) // save regs
+ bis r25, r31, r16 // a0 <- va
+
+ stq r17, osfsf_a1(sp) // a1
+ srl r13, 1, r17 // shift fault bits to right position
+
+ stq r11, osfsf_ps(sp) // save old ps
+ bis r12, r31, r11 // update ps
+
+ stq r14, osfsf_pc(sp) // save pc
+ mfpr r25, pt_entmm // get entry point
+
+ stq r29, osfsf_gp(sp) // save gp
+ cmovlbs r17, 1, r17 // a2. acv overrides fox.
+
+ mtpr r25, exc_addr // load exc_addr with entMM
+ // 1 cycle to hw_rei
+ mfpr r29, pt_kgp // get the kgp
+
+ hw_rei_spe // done
+
+//
+//unalign_trap_cont
+// An unalign trap has been taken. Just need to finish up a few things.
+//
+// Current state:
+// r25 - entUna
+// r13 - shifted MMstat
+//
+//
+ ALIGN_BLOCK
+unalign_trap_cont:
+ mtpr r25, exc_addr // load exc_addr with entUna
+ // 1 cycle to hw_rei
+
+
+ mfpr r29, pt_kgp // get the kgp
+ and r13, mm_stat_m_ra, r18 // Clean Ra for a2
+
+ hw_rei_spe // done
+
+
+
+//
+// dfault_in_pal
+// Dfault trap was taken, exc_addr points to a PAL PC.
+// r9 - mmstat<opcode> right justified
+// r8 - exception address
+//
+// These are the cases:
+// opcode was STQ -- from a stack builder, KSP not valid halt
+// r14 - original exc_addr
+// r11 - original PS
+// opcode was STL_C -- rti or retsys clear lock_flag by stack write,
+// KSP not valid halt
+// r11 - original PS
+// r14 - original exc_addr
+// opcode was LDQ -- retsys or rti stack read, KSP not valid halt
+// r11 - original PS
+// r14 - original exc_addr
+// opcode was HW_LD -- itbmiss or dtbmiss, bugcheck due to fault on page tables
+// r10 - original exc_addr
+// r11 - original PS
+//
+//
+//
+ ALIGN_BLOCK
+dfault_in_pal:
+ DEBUGSTORE(0x50)
+ bic r8, 3, r8 // Clean PC
+ mfpr r9, pal_base
+
+ mfpr r31, va // unlock VA
+
+ // if not real_mm, should never get here from miss flows
+
+ subq r9, r8, r8 // pal_base - offset
+
+ lda r9, pal_itb_ldq-pal_base(r8)
+ nop
+
+ beq r9, dfault_do_bugcheck
+ lda r9, pal_dtb_ldq-pal_base(r8)
+
+ beq r9, dfault_do_bugcheck
+
+//
+// KSP invalid halt case --
+ksp_inval_halt:
+ DEBUGSTORE(76)
+ bic r11, osfps_m_mode, r11 // set ps to kernel mode
+ mtpr r0, pt0
+
+ mtpr r31, dtb_cm // Make sure that the CM IPRs are all kernel mode
+ mtpr r31, ips
+
+ mtpr r14, exc_addr // Set PC to instruction that caused trouble
+ bsr r0, pal_update_pcb // update the pcb
+
+ lda r0, hlt_c_ksp_inval(r31) // set halt code to hw halt
+ br r31, sys_enter_console // enter the console
+
+ ALIGN_BRANCH
+dfault_do_bugcheck:
+ bis r10, r31, r14 // bugcheck expects exc_addr in r14
+ br r31, pal_pal_bug_check
+
+
+//
+// dfault_fetch_ldr31_err - ignore faults on fetch(m) and loads to r31/f31
+// On entry -
+// r14 - exc_addr
+// VA is locked
+//
+//
+ ALIGN_BLOCK
+dfault_fetch_ldr31_err:
+ mtpr r11, ev5__dtb_cm
+ mtpr r11, ev5__ps // Make sure ps hasn't changed
+
+ mfpr r31, va // unlock the mbox
+ addq r14, 4, r14 // inc the pc to skip the fetch
+
+ mtpr r14, exc_addr // give ibox new PC
+ mfpr r31, pt0 // pad exc_addr write
+
+ hw_rei
+
+
+
+ ALIGN_BLOCK
+//
+// sys_from_kern
+// callsys from kernel mode - OS bugcheck machine check
+//
+//
+sys_from_kern:
+ mfpr r14, exc_addr // PC points to call_pal
+ subq r14, 4, r14
+
+ lda r25, mchk_c_os_bugcheck(r31) // fetch mchk code
+ br r31, pal_pal_mchk
+
+
+// Continuation of long call_pal flows
+//
+// wrent_tbl
+// Table to write *int in paltemps.
+// 4 instructions/entry
+// r16 has new value
+//
+//
+ ALIGN_BLOCK
+wrent_tbl:
+//orig pvc_jsr wrent, dest=1
+ nop
+ mtpr r16, pt_entint
+
+ mfpr r31, pt0 // Pad for mt->mf paltemp rule
+ hw_rei
+
+
+//orig pvc_jsr wrent, dest=1
+ nop
+ mtpr r16, pt_entarith
+
+ mfpr r31, pt0 // Pad for mt->mf paltemp rule
+ hw_rei
+
+
+//orig pvc_jsr wrent, dest=1
+ nop
+ mtpr r16, pt_entmm
+
+ mfpr r31, pt0 // Pad for mt->mf paltemp rule
+ hw_rei
+
+
+//orig pvc_jsr wrent, dest=1
+ nop
+ mtpr r16, pt_entif
+
+ mfpr r31, pt0 // Pad for mt->mf paltemp rule
+ hw_rei
+
+
+//orig pvc_jsr wrent, dest=1
+ nop
+ mtpr r16, pt_entuna
+
+ mfpr r31, pt0 // Pad for mt->mf paltemp rule
+ hw_rei
+
+
+//orig pvc_jsr wrent, dest=1
+ nop
+ mtpr r16, pt_entsys
+
+ mfpr r31, pt0 // Pad for mt->mf paltemp rule
+ hw_rei
+
+ ALIGN_BLOCK
+//
+// tbi_tbl
+// Table to do tbi instructions
+// 4 instructions per entry
+//
+tbi_tbl:
+ // -2 tbia
+//orig pvc_jsr tbi, dest=1
+ mtpr r31, ev5__dtb_ia // Flush DTB
+ mtpr r31, ev5__itb_ia // Flush ITB
+
+ hw_rei_stall
+
+ nop // Pad table
+
+ // -1 tbiap
+//orig pvc_jsr tbi, dest=1
+ mtpr r31, ev5__dtb_iap // Flush DTB
+ mtpr r31, ev5__itb_iap // Flush ITB
+
+ hw_rei_stall
+
+ nop // Pad table
+
+
+ // 0 unused
+//orig pvc_jsr tbi, dest=1
+ hw_rei // Pad table
+ nop
+ nop
+ nop
+
+
+ // 1 tbisi
+//orig pvc_jsr tbi, dest=1
+
+ nop
+ nop
+ mtpr r17, ev5__itb_is // Flush ITB
+ hw_rei_stall
+
+ // 2 tbisd
+//orig pvc_jsr tbi, dest=1
+ mtpr r17, ev5__dtb_is // Flush DTB.
+ nop
+
+ nop
+ hw_rei_stall
+
+
+ // 3 tbis
+//orig pvc_jsr tbi, dest=1
+ mtpr r17, ev5__dtb_is // Flush DTB
+ br r31, tbi_finish
+ ALIGN_BRANCH
+tbi_finish:
+ mtpr r17, ev5__itb_is // Flush ITB
+ hw_rei_stall
+
+
+
+ ALIGN_BLOCK
+//
+// bpt_bchk_common:
+// Finish up the bpt/bchk instructions
+//
+bpt_bchk_common:
+ stq r18, osfsf_a2(sp) // a2
+ mfpr r13, pt_entif // get entry point
+
+ stq r12, osfsf_ps(sp) // save old ps
+ stq r14, osfsf_pc(sp) // save pc
+
+ stq r29, osfsf_gp(sp) // save gp
+ mtpr r13, exc_addr // load exc_addr with entIF
+ // 1 cycle to hw_rei
+
+ mfpr r29, pt_kgp // get the kgp
+
+
+ hw_rei_spe // done
+
+
+ ALIGN_BLOCK
+//
+// rti_to_user
+// Finish up the rti instruction
+//
+rti_to_user:
+ mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
+ mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
+
+ mtpr r31, ev5__ipl // set the ipl. No hw_rei for 2 cycles
+ mtpr r25, pt_ksp // save off incase RTI to user
+
+ mfpr r30, pt_usp
+ hw_rei_spe // and back
+
+
+ ALIGN_BLOCK
+//
+// rti_to_kern
+// Finish up the rti instruction
+//
+rti_to_kern:
+ and r12, osfps_m_ipl, r11 // clean ps
+ mfpr r12, pt_intmask // get int mask
+
+ extbl r12, r11, r12 // get mask for this ipl
+ mtpr r25, pt_ksp // save off incase RTI to user
+
+ mtpr r12, ev5__ipl // set the new ipl.
+ or r25, r31, sp // sp
+
+// pvc_violate 217 // possible hidden mt->mf ipl not a problem in callpals
+ hw_rei
+
+ ALIGN_BLOCK
+//
+// swpctx_cont
+// Finish up the swpctx instruction
+//
+
+swpctx_cont:
+
+ bic r25, r24, r25 // clean icsr<FPE,PMP>
+ sll r12, icsr_v_fpe, r12 // shift new fen to pos
+
+ ldq_p r14, osfpcb_q_mmptr(r16)// get new mmptr
+ srl r22, osfpcb_v_pme, r22 // get pme down to bit 0
+
+ or r25, r12, r25 // icsr with new fen
+ srl r23, 32, r24 // move asn to low asn pos
+
+ and r22, 1, r22
+ sll r24, itb_asn_v_asn, r12
+
+ sll r22, icsr_v_pmp, r22
+ nop
+
+ or r25, r22, r25 // icsr with new pme
+
+ sll r24, dtb_asn_v_asn, r24
+
+ subl r23, r13, r13 // gen new cc offset
+ mtpr r12, itb_asn // no hw_rei_stall in 0,1,2,3,4
+
+ mtpr r24, dtb_asn // Load up new ASN
+ mtpr r25, icsr // write the icsr
+
+ sll r14, page_offset_size_bits, r14 // Move PTBR into internal position.
+ ldq_p r25, osfpcb_q_usp(r16) // get new usp
+
+ insll r13, 4, r13 // >> 32
+// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow
+ mtpr r14, pt_ptbr // load the new ptbr
+
+ mtpr r13, cc // set new offset
+ ldq_p r30, osfpcb_q_ksp(r16) // get new ksp
+
+// pvc_violate 379 // ldq_p can't trap except replay. only problem if mf same ipr in same shadow
+ mtpr r25, pt_usp // save usp
+
+no_pm_change_10_: hw_rei_stall // back we go
+
+ ALIGN_BLOCK
+//
+// swppal_cont - finish up the swppal call_pal
+//
+
+swppal_cont:
+ mfpr r2, pt_misc // get misc bits
+ sll r0, pt_misc_v_switch, r0 // get the "I've switched" bit
+ or r2, r0, r2 // set the bit
+ mtpr r31, ev5__alt_mode // ensure alt_mode set to 0 (kernel)
+ mtpr r2, pt_misc // update the chip
+
+ or r3, r31, r4
+ mfpr r3, pt_impure // pass pointer to the impure area in r3
+//orig fix_impure_ipr r3 // adjust impure pointer for ipr read
+//orig restore_reg1 bc_ctl, r1, r3, ipr=1 // pass cns_bc_ctl in r1
+//orig restore_reg1 bc_config, r2, r3, ipr=1 // pass cns_bc_config in r2
+//orig unfix_impure_ipr r3 // restore impure pointer
+ lda r3, CNS_Q_IPR(r3)
+ RESTORE_SHADOW(r1,CNS_Q_BC_CTL,r3);
+ RESTORE_SHADOW(r1,CNS_Q_BC_CFG,r3);
+ lda r3, -CNS_Q_IPR(r3)
+
+ or r31, r31, r0 // set status to success
+// pvc_violate 1007
+ jmp r31, (r4) // and call our friend, it's her problem now
+
+
+swppal_fail:
+ addq r0, 1, r0 // set unknown pal or not loaded
+ hw_rei // and return
+
+
+// .sbttl "Memory management"
+
+ ALIGN_BLOCK
+//
+//foe_ipte_handler
+// IFOE detected on level 3 pte, sort out FOE vs ACV
+//
+// on entry:
+// with
+// R8 = pte
+// R10 = pc
+//
+// Function
+// Determine TNV vs ACV vs FOE. Build stack and dispatch
+// Will not be here if TNV.
+//
+
+foe_ipte_handler:
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ bis r11, r31, r12 // Save PS for stack write
+ bge r25, foe_ipte_handler_10_ // no stack swap needed if cm=kern
+
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r11 // Set new PS
+ mfpr r30, pt_ksp
+
+ srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern
+ nop
+
+foe_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0>
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+
+ or r10, r31, r14 // Save pc/va in case TBmiss or fault on stack
+ mfpr r13, pt_entmm // get entry point
+
+ stq r16, osfsf_a0(sp) // a0
+ or r14, r31, r16 // pass pc/va as a0
+
+ stq r17, osfsf_a1(sp) // a1
+ nop
+
+ stq r18, osfsf_a2(sp) // a2
+ lda r17, mmcsr_c_acv(r31) // assume ACV
+
+ stq r16, osfsf_pc(sp) // save pc
+ cmovlbs r25, mmcsr_c_foe, r17 // otherwise FOE
+
+ stq r12, osfsf_ps(sp) // save ps
+ subq r31, 1, r18 // pass flag of istream as a2
+
+ stq r29, osfsf_gp(sp)
+ mtpr r13, exc_addr // set vector address
+
+ mfpr r29, pt_kgp // load kgp
+ hw_rei_spe // out to exec
+
+ ALIGN_BLOCK
+//
+//invalid_ipte_handler
+// TNV detected on level 3 pte, sort out TNV vs ACV
+//
+// on entry:
+// with
+// R8 = pte
+// R10 = pc
+//
+// Function
+// Determine TNV vs ACV. Build stack and dispatch.
+//
+
+invalid_ipte_handler:
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ bis r11, r31, r12 // Save PS for stack write
+ bge r25, invalid_ipte_handler_10_ // no stack swap needed if cm=kern
+
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r11 // Set new PS
+ mfpr r30, pt_ksp
+
+ srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern
+ nop
+
+invalid_ipte_handler_10_: srl r8, osfpte_v_kre, r25 // get kre to <0>
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+
+ or r10, r31, r14 // Save pc/va in case TBmiss on stack
+ mfpr r13, pt_entmm // get entry point
+
+ stq r16, osfsf_a0(sp) // a0
+ or r14, r31, r16 // pass pc/va as a0
+
+ stq r17, osfsf_a1(sp) // a1
+ nop
+
+ stq r18, osfsf_a2(sp) // a2
+ and r25, 1, r17 // Isolate kre
+
+ stq r16, osfsf_pc(sp) // save pc
+ xor r17, 1, r17 // map to acv/tnv as a1
+
+ stq r12, osfsf_ps(sp) // save ps
+ subq r31, 1, r18 // pass flag of istream as a2
+
+ stq r29, osfsf_gp(sp)
+ mtpr r13, exc_addr // set vector address
+
+ mfpr r29, pt_kgp // load kgp
+ hw_rei_spe // out to exec
+
+
+
+
+ ALIGN_BLOCK
+//
+//invalid_dpte_handler
+// INVALID detected on level 3 pte, sort out TNV vs ACV
+//
+// on entry:
+// with
+// R10 = va
+// R8 = pte
+// R9 = mm_stat
+// PT6 = pc
+//
+// Function
+// Determine TNV vs ACV. Build stack and dispatch
+//
+
+
+invalid_dpte_handler:
+ mfpr r12, pt6
+ blbs r12, tnv_in_pal // Special handler if original faulting reference was in PALmode
+
+ bis r12, r31, r14 // save PC in case of tbmiss or fault
+ srl r9, mm_stat_v_opcode, r25 // shift opc to <0>
+
+ mtpr r11, pt0 // Save PS for stack write
+ and r25, mm_stat_m_opcode, r25 // isolate opcode
+
+ cmpeq r25, evx_opc_sync, r25 // is it FETCH/FETCH_M?
+ blbs r25, nmiss_fetch_ldr31_err // yes
+
+ //dismiss exception if load to r31/f31
+ blbs r9, invalid_dpte_no_dismiss // mm_stat<0> set on store or fetchm
+
+ // not a store or fetch, must be a load
+ srl r9, mm_stat_v_ra, r25 // Shift rnum to low bits
+
+ and r25, 0x1F, r25 // isolate rnum
+ nop
+
+ cmpeq r25, 0x1F, r25 // Is the rnum r31 or f31?
+ bne r25, nmiss_fetch_ldr31_err // Yes, dismiss the fault
+
+invalid_dpte_no_dismiss:
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ bge r25, invalid_dpte_no_dismiss_10_ // no stack swap needed if cm=kern
+
+ srl r8, osfpte_v_ure-osfpte_v_kre, r8 // move pte user bits to kern
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r11 // Set new PS
+ mfpr r30, pt_ksp
+
+invalid_dpte_no_dismiss_10_: srl r8, osfpte_v_kre, r12 // get kre to <0>
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+
+ or r10, r31, r25 // Save va in case TBmiss on stack
+ and r9, 1, r13 // save r/w flag
+
+ stq r16, osfsf_a0(sp) // a0
+ or r25, r31, r16 // pass va as a0
+
+ stq r17, osfsf_a1(sp) // a1
+ or r31, mmcsr_c_acv, r17 // assume acv
+
+ srl r12, osfpte_v_kwe-osfpte_v_kre, r25 // get write enable to <0>
+ stq r29, osfsf_gp(sp)
+
+ stq r18, osfsf_a2(sp) // a2
+ cmovlbs r13, r25, r12 // if write access move acv based on write enable
+
+ or r13, r31, r18 // pass flag of dstream access and read vs write
+ mfpr r25, pt0 // get ps
+
+ stq r14, osfsf_pc(sp) // save pc
+ mfpr r13, pt_entmm // get entry point
+
+ stq r25, osfsf_ps(sp) // save ps
+ mtpr r13, exc_addr // set vector address
+
+ mfpr r29, pt_kgp // load kgp
+ cmovlbs r12, mmcsr_c_tnv, r17 // make p2 be tnv if access ok else acv
+
+ hw_rei_spe // out to exec
+
+//
+//
+// We come here if we are erring on a dtb_miss, and the instr is a
+// fetch, fetch_m, of load to r31/f31.
+// The PC is incremented, and we return to the program.
+// essentially ignoring the instruction and error.
+//
+//
+ ALIGN_BLOCK
+nmiss_fetch_ldr31_err:
+ mfpr r12, pt6
+ addq r12, 4, r12 // bump pc to pc+4
+
+ mtpr r12, exc_addr // and set entry point
+ mfpr r31, pt0 // pad exc_addr write
+
+ hw_rei //
+
+ ALIGN_BLOCK
+//
+// double_pte_inv
+// We had a single tbmiss which turned into a double tbmiss which found
+// an invalid PTE. Return to single miss with a fake pte, and the invalid
+// single miss flow will report the error.
+//
+// on entry:
+// r21 PTE
+// r22 available
+// VA IPR locked with original fault VA
+// pt4 saved r21
+// pt5 saved r22
+// pt6 original exc_addr
+//
+// on return to tbmiss flow:
+// r8 fake PTE
+//
+//
+//
+double_pte_inv:
+ srl r21, osfpte_v_kre, r21 // get the kre bit to <0>
+ mfpr r22, exc_addr // get the pc
+
+ lda r22, 4(r22) // inc the pc
+ lda r8, osfpte_m_prot(r31) // make a fake pte with xre and xwe set
+
+ cmovlbc r21, r31, r8 // set to all 0 for acv if pte<kre> is 0
+ mtpr r22, exc_addr // set for rei
+
+ mfpr r21, pt4 // restore regs
+ mfpr r22, pt5 // restore regs
+
+ hw_rei // back to tb miss
+
+ ALIGN_BLOCK
+//
+//tnv_in_pal
+// The only places in pal that ld or store are the
+// stack builders, rti or retsys. Any of these mean we
+// need to take a ksp not valid halt.
+//
+//
+tnv_in_pal:
+
+
+ br r31, ksp_inval_halt
+
+
+// .sbttl "Icache flush routines"
+
+ ALIGN_BLOCK
+//
+// Common Icache flush routine.
+//
+//
+//
+pal_ic_flush:
+ nop
+ mtpr r31, ev5__ic_flush_ctl // Icache flush - E1
+ nop
+ nop
+
+// Now, do 44 NOPs. 3RFB prefetches (24) + IC buffer,IB,slot,issue (20)
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop // 10
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop // 20
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop // 30
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop // 40
+
+ nop
+ nop
+
+one_cycle_and_hw_rei:
+ nop
+ nop
+
+ hw_rei_stall
+
+ ALIGN_BLOCK
+//
+//osfpal_calpal_opcdec
+// Here for all opcdec CALL_PALs
+//
+// Build stack frame
+// a0 <- code
+// a1 <- unpred
+// a2 <- unpred
+// vector via entIF
+//
+//
+
+osfpal_calpal_opcdec:
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ mfpr r14, exc_addr // get pc
+ nop
+
+ bis r11, r31, r12 // Save PS for stack write
+ bge r25, osfpal_calpal_opcdec_10_ // no stack swap needed if cm=kern
+
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r11 // Set new PS
+ mfpr r30, pt_ksp
+
+osfpal_calpal_opcdec_10_:
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+ nop
+
+ stq r16, osfsf_a0(sp) // save regs
+ bis r31, osf_a0_opdec, r16 // set a0
+
+ stq r18, osfsf_a2(sp) // a2
+ mfpr r13, pt_entif // get entry point
+
+ stq r12, osfsf_ps(sp) // save old ps
+ stq r17, osfsf_a1(sp) // a1
+
+ stq r14, osfsf_pc(sp) // save pc
+ nop
+
+ stq r29, osfsf_gp(sp) // save gp
+ mtpr r13, exc_addr // load exc_addr with entIF
+ // 1 cycle to hw_rei
+
+ mfpr r29, pt_kgp // get the kgp
+
+
+ hw_rei_spe // done
+
+
+
+
+
+//
+//pal_update_pcb
+// Update the PCB with the current SP, AST, and CC info
+//
+// r0 - return linkage
+//
+ ALIGN_BLOCK
+
+pal_update_pcb:
+ mfpr r12, pt_pcbb // get pcbb
+ and r11, osfps_m_mode, r25 // get mode
+ beq r25, pal_update_pcb_10_ // in kern? no need to update user sp
+ mtpr r30, pt_usp // save user stack
+ stq_p r30, osfpcb_q_usp(r12) // store usp
+ br r31, pal_update_pcb_20_ // join common
+pal_update_pcb_10_: stq_p r30, osfpcb_q_ksp(r12) // store ksp
+pal_update_pcb_20_: rpcc r13 // get cyccounter
+ srl r13, 32, r14 // move offset
+ addl r13, r14, r14 // merge for new time
+ stl_p r14, osfpcb_l_cc(r12) // save time
+
+//orig pvc_jsr updpcb, bsr=1, dest=1
+ ret r31, (r0)
+
+
+//
+// pal_save_state
+//
+// Function
+// All chip state saved, all PT's, SR's FR's, IPR's
+//
+//
+// Regs' on entry...
+//
+// R0 = halt code
+// pt0 = r0
+// R1 = pointer to impure
+// pt4 = r1
+// R3 = return addr
+// pt5 = r3
+//
+// register usage:
+// r0 = halt_code
+// r1 = addr of impure area
+// r3 = return_address
+// r4 = scratch
+//
+//
+
+ ALIGN_BLOCK
+ .globl pal_save_state
+pal_save_state:
+//
+//
+// start of implementation independent save routine
+//
+// the impure area is larger than the addressibility of hw_ld and hw_st
+// therefore, we need to play some games: The impure area
+// is informally divided into the "machine independent" part and the
+// "machine dependent" part. The state that will be saved in the
+// "machine independent" part are gpr's, fpr's, hlt, flag, mchkflag (use (un)fix_impure_gpr macros).
+// All others will be in the "machine dependent" part (use (un)fix_impure_ipr macros).
+// The impure pointer will need to be adjusted by a different offset for each. The store/restore_reg
+// macros will automagically adjust the offset correctly.
+//
+
+// The distributed code is commented out and followed by corresponding SRC code.
+// Beware: SAVE_IPR and RESTORE_IPR blow away r0(v0)
+
+//orig fix_impure_gpr r1 // adjust impure area pointer for stores to "gpr" part of impure area
+ lda r1, 0x200(r1) // Point to center of CPU segment
+//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area flag
+ SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the valid flag
+//orig store_reg1 hlt, r0, r1, ipr=1
+ SAVE_GPR(r0,CNS_Q_HALT,r1) // Save the halt code
+
+ mfpr r0, pt0 // get r0 back //orig
+//orig store_reg1 0, r0, r1 // save r0
+ SAVE_GPR(r0,CNS_Q_GPR+0x00,r1) // Save r0
+
+ mfpr r0, pt4 // get r1 back //orig
+//orig store_reg1 1, r0, r1 // save r1
+ SAVE_GPR(r0,CNS_Q_GPR+0x08,r1) // Save r1
+
+//orig store_reg 2 // save r2
+ SAVE_GPR(r2,CNS_Q_GPR+0x10,r1) // Save r2
+
+ mfpr r0, pt5 // get r3 back //orig
+//orig store_reg1 3, r0, r1 // save r3
+ SAVE_GPR(r0,CNS_Q_GPR+0x18,r1) // Save r3
+
+ // reason code has been saved
+ // r0 has been saved
+ // r1 has been saved
+ // r2 has been saved
+ // r3 has been saved
+ // pt0, pt4, pt5 have been lost
+
+ //
+ // Get out of shadow mode
+ //
+
+ mfpr r2, icsr // Get icsr
+ ldah r0, (1<<(icsr_v_sde-16))(r31)
+ bic r2, r0, r0 // ICSR with SDE clear
+ mtpr r0, icsr // Turn off SDE
+
+ mfpr r31, pt0 // SDE bubble cycle 1
+ mfpr r31, pt0 // SDE bubble cycle 2
+ mfpr r31, pt0 // SDE bubble cycle 3
+ nop
+
+
+ // save integer regs R4-r31
+ SAVE_GPR(r4,CNS_Q_GPR+0x20,r1)
+ SAVE_GPR(r5,CNS_Q_GPR+0x28,r1)
+ SAVE_GPR(r6,CNS_Q_GPR+0x30,r1)
+ SAVE_GPR(r7,CNS_Q_GPR+0x38,r1)
+ SAVE_GPR(r8,CNS_Q_GPR+0x40,r1)
+ SAVE_GPR(r9,CNS_Q_GPR+0x48,r1)
+ SAVE_GPR(r10,CNS_Q_GPR+0x50,r1)
+ SAVE_GPR(r11,CNS_Q_GPR+0x58,r1)
+ SAVE_GPR(r12,CNS_Q_GPR+0x60,r1)
+ SAVE_GPR(r13,CNS_Q_GPR+0x68,r1)
+ SAVE_GPR(r14,CNS_Q_GPR+0x70,r1)
+ SAVE_GPR(r15,CNS_Q_GPR+0x78,r1)
+ SAVE_GPR(r16,CNS_Q_GPR+0x80,r1)
+ SAVE_GPR(r17,CNS_Q_GPR+0x88,r1)
+ SAVE_GPR(r18,CNS_Q_GPR+0x90,r1)
+ SAVE_GPR(r19,CNS_Q_GPR+0x98,r1)
+ SAVE_GPR(r20,CNS_Q_GPR+0xA0,r1)
+ SAVE_GPR(r21,CNS_Q_GPR+0xA8,r1)
+ SAVE_GPR(r22,CNS_Q_GPR+0xB0,r1)
+ SAVE_GPR(r23,CNS_Q_GPR+0xB8,r1)
+ SAVE_GPR(r24,CNS_Q_GPR+0xC0,r1)
+ SAVE_GPR(r25,CNS_Q_GPR+0xC8,r1)
+ SAVE_GPR(r26,CNS_Q_GPR+0xD0,r1)
+ SAVE_GPR(r27,CNS_Q_GPR+0xD8,r1)
+ SAVE_GPR(r28,CNS_Q_GPR+0xE0,r1)
+ SAVE_GPR(r29,CNS_Q_GPR+0xE8,r1)
+ SAVE_GPR(r30,CNS_Q_GPR+0xF0,r1)
+ SAVE_GPR(r31,CNS_Q_GPR+0xF8,r1)
+
+ // save all paltemp regs except pt0
+
+//orig unfix_impure_gpr r1 // adjust impure area pointer for gpr stores
+//orig fix_impure_ipr r1 // adjust impure area pointer for pt stores
+
+ lda r1, -0x200(r1) // Restore the impure base address.
+ lda r1, CNS_Q_IPR(r1) // Point to the base of IPR area.
+ SAVE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle
+ SAVE_IPR(pt1,CNS_Q_PT+0x08,r1)
+ SAVE_IPR(pt2,CNS_Q_PT+0x10,r1)
+ SAVE_IPR(pt3,CNS_Q_PT+0x18,r1)
+ SAVE_IPR(pt4,CNS_Q_PT+0x20,r1)
+ SAVE_IPR(pt5,CNS_Q_PT+0x28,r1)
+ SAVE_IPR(pt6,CNS_Q_PT+0x30,r1)
+ SAVE_IPR(pt7,CNS_Q_PT+0x38,r1)
+ SAVE_IPR(pt8,CNS_Q_PT+0x40,r1)
+ SAVE_IPR(pt9,CNS_Q_PT+0x48,r1)
+ SAVE_IPR(pt10,CNS_Q_PT+0x50,r1)
+ SAVE_IPR(pt11,CNS_Q_PT+0x58,r1)
+ SAVE_IPR(pt12,CNS_Q_PT+0x60,r1)
+ SAVE_IPR(pt13,CNS_Q_PT+0x68,r1)
+ SAVE_IPR(pt14,CNS_Q_PT+0x70,r1)
+ SAVE_IPR(pt15,CNS_Q_PT+0x78,r1)
+ SAVE_IPR(pt16,CNS_Q_PT+0x80,r1)
+ SAVE_IPR(pt17,CNS_Q_PT+0x88,r1)
+ SAVE_IPR(pt18,CNS_Q_PT+0x90,r1)
+ SAVE_IPR(pt19,CNS_Q_PT+0x98,r1)
+ SAVE_IPR(pt20,CNS_Q_PT+0xA0,r1)
+ SAVE_IPR(pt21,CNS_Q_PT+0xA8,r1)
+ SAVE_IPR(pt22,CNS_Q_PT+0xB0,r1)
+ SAVE_IPR(pt23,CNS_Q_PT+0xB8,r1)
+
+ // Restore shadow mode
+ mfpr r31, pt0 // pad write to icsr out of shadow of store (trap does not abort write)
+ mfpr r31, pt0
+ mtpr r2, icsr // Restore original ICSR
+
+ mfpr r31, pt0 // SDE bubble cycle 1
+ mfpr r31, pt0 // SDE bubble cycle 2
+ mfpr r31, pt0 // SDE bubble cycle 3
+ nop
+
+ // save all integer shadow regs
+ SAVE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code
+ SAVE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1)
+ SAVE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1)
+ SAVE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1)
+ SAVE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1)
+ SAVE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1)
+ SAVE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1)
+ SAVE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1)
+
+ SAVE_IPR(excAddr,CNS_Q_EXC_ADDR,r1)
+ SAVE_IPR(palBase,CNS_Q_PAL_BASE,r1)
+ SAVE_IPR(mmStat,CNS_Q_MM_STAT,r1)
+ SAVE_IPR(va,CNS_Q_VA,r1)
+ SAVE_IPR(icsr,CNS_Q_ICSR,r1)
+ SAVE_IPR(ipl,CNS_Q_IPL,r1)
+ SAVE_IPR(ips,CNS_Q_IPS,r1)
+ SAVE_IPR(itbAsn,CNS_Q_ITB_ASN,r1)
+ SAVE_IPR(aster,CNS_Q_ASTER,r1)
+ SAVE_IPR(astrr,CNS_Q_ASTRR,r1)
+ SAVE_IPR(sirr,CNS_Q_SIRR,r1)
+ SAVE_IPR(isr,CNS_Q_ISR,r1)
+ SAVE_IPR(iVptBr,CNS_Q_IVPTBR,r1)
+ SAVE_IPR(mcsr,CNS_Q_MCSR,r1)
+ SAVE_IPR(dcMode,CNS_Q_DC_MODE,r1)
+
+//orig pvc_violate 379 // mf maf_mode after a store ok (pvc doesn't distinguish ld from st)
+//orig store_reg maf_mode, ipr=1 // save ipr -- no mbox instructions for
+//orig // PVC violation applies only to
+pvc$osf35$379: // loads. HW_ST ok here, so ignore
+ SAVE_IPR(mafMode,CNS_Q_MAF_MODE,r1) // MBOX INST->MF MAF_MODE IN 0,1,2
+
+
+ //the following iprs are informational only -- will not be restored
+
+ SAVE_IPR(icPerr,CNS_Q_ICPERR_STAT,r1)
+ SAVE_IPR(PmCtr,CNS_Q_PM_CTR,r1)
+ SAVE_IPR(intId,CNS_Q_INT_ID,r1)
+ SAVE_IPR(excSum,CNS_Q_EXC_SUM,r1)
+ SAVE_IPR(excMask,CNS_Q_EXC_MASK,r1)
+ ldah r14, 0xFFF0(zero)
+ zap r14, 0xE0, r14 // Get base address of CBOX IPRs
+ NOP // Pad mfpr dcPerr out of shadow of
+ NOP // last store
+ NOP
+ SAVE_IPR(dcPerr,CNS_Q_DCPERR_STAT,r1)
+
+ // read cbox ipr state
+
+ mb
+ ldq_p r2, scCtl(r14)
+ ldq_p r13, ldLock(r14)
+ ldq_p r4, scAddr(r14)
+ ldq_p r5, eiAddr(r14)
+ ldq_p r6, bcTagAddr(r14)
+ ldq_p r7, fillSyn(r14)
+ bis r5, r4, zero // Make sure all loads complete before
+ bis r7, r6, zero // reading registers that unlock them.
+ ldq_p r8, scStat(r14) // Unlocks scAddr.
+ ldq_p r9, eiStat(r14) // Unlocks eiAddr, bcTagAddr, fillSyn.
+ ldq_p zero, eiStat(r14) // Make sure it is really unlocked.
+ mb
+
+ // save cbox ipr state
+ SAVE_SHADOW(r2,CNS_Q_SC_CTL,r1);
+ SAVE_SHADOW(r13,CNS_Q_LD_LOCK,r1);
+ SAVE_SHADOW(r4,CNS_Q_SC_ADDR,r1);
+ SAVE_SHADOW(r5,CNS_Q_EI_ADDR,r1);
+ SAVE_SHADOW(r6,CNS_Q_BC_TAG_ADDR,r1);
+ SAVE_SHADOW(r7,CNS_Q_FILL_SYN,r1);
+ SAVE_SHADOW(r8,CNS_Q_SC_STAT,r1);
+ SAVE_SHADOW(r9,CNS_Q_EI_STAT,r1);
+ //bc_config? sl_rcv?
+
+// restore impure base
+//orig unfix_impure_ipr r1
+ lda r1, -CNS_Q_IPR(r1)
+
+// save all floating regs
+ mfpr r0, icsr // get icsr
+ or r31, 1, r2 // get a one
+ sll r2, icsr_v_fpe, r2 // Shift it into ICSR<FPE> position
+ or r2, r0, r0 // set FEN on
+ mtpr r0, icsr // write to icsr, enabling FEN
+
+// map the save area virtually
+ mtpr r31, dtbIa // Clear all DTB entries
+ srl r1, va_s_off, r0 // Clean off byte-within-page offset
+ sll r0, pte_v_pfn, r0 // Shift to form PFN
+ lda r0, pte_m_prot(r0) // Set all read/write enable bits
+ mtpr r0, dtbPte // Load the PTE and set valid
+ mtpr r1, dtbTag // Write the PTE and tag into the DTB
+
+
+// map the next page too - in case the impure area crosses a page boundary
+ lda r4, (1<<va_s_off)(r1) // Generate address for next page
+ srl r4, va_s_off, r0 // Clean off byte-within-page offset
+ sll r0, pte_v_pfn, r0 // Shift to form PFN
+ lda r0, pte_m_prot(r0) // Set all read/write enable bits
+ mtpr r0, dtbPte // Load the PTE and set valid
+ mtpr r4, dtbTag // Write the PTE and tag into the DTB
+
+ sll r31, 0, r31 // stall cycle 1
+ sll r31, 0, r31 // stall cycle 2
+ sll r31, 0, r31 // stall cycle 3
+ nop
+
+// add offset for saving fpr regs
+//orig fix_impure_gpr r1
+ lda r1, 0x200(r1) // Point to center of CPU segment
+
+// now save the regs - F0-F31
+ mf_fpcr f0 // original
+
+ SAVE_FPR(f0,CNS_Q_FPR+0x00,r1)
+ SAVE_FPR(f1,CNS_Q_FPR+0x08,r1)
+ SAVE_FPR(f2,CNS_Q_FPR+0x10,r1)
+ SAVE_FPR(f3,CNS_Q_FPR+0x18,r1)
+ SAVE_FPR(f4,CNS_Q_FPR+0x20,r1)
+ SAVE_FPR(f5,CNS_Q_FPR+0x28,r1)
+ SAVE_FPR(f6,CNS_Q_FPR+0x30,r1)
+ SAVE_FPR(f7,CNS_Q_FPR+0x38,r1)
+ SAVE_FPR(f8,CNS_Q_FPR+0x40,r1)
+ SAVE_FPR(f9,CNS_Q_FPR+0x48,r1)
+ SAVE_FPR(f10,CNS_Q_FPR+0x50,r1)
+ SAVE_FPR(f11,CNS_Q_FPR+0x58,r1)
+ SAVE_FPR(f12,CNS_Q_FPR+0x60,r1)
+ SAVE_FPR(f13,CNS_Q_FPR+0x68,r1)
+ SAVE_FPR(f14,CNS_Q_FPR+0x70,r1)
+ SAVE_FPR(f15,CNS_Q_FPR+0x78,r1)
+ SAVE_FPR(f16,CNS_Q_FPR+0x80,r1)
+ SAVE_FPR(f17,CNS_Q_FPR+0x88,r1)
+ SAVE_FPR(f18,CNS_Q_FPR+0x90,r1)
+ SAVE_FPR(f19,CNS_Q_FPR+0x98,r1)
+ SAVE_FPR(f20,CNS_Q_FPR+0xA0,r1)
+ SAVE_FPR(f21,CNS_Q_FPR+0xA8,r1)
+ SAVE_FPR(f22,CNS_Q_FPR+0xB0,r1)
+ SAVE_FPR(f23,CNS_Q_FPR+0xB8,r1)
+ SAVE_FPR(f24,CNS_Q_FPR+0xC0,r1)
+ SAVE_FPR(f25,CNS_Q_FPR+0xC8,r1)
+ SAVE_FPR(f26,CNS_Q_FPR+0xD0,r1)
+ SAVE_FPR(f27,CNS_Q_FPR+0xD8,r1)
+ SAVE_FPR(f28,CNS_Q_FPR+0xE0,r1)
+ SAVE_FPR(f29,CNS_Q_FPR+0xE8,r1)
+ SAVE_FPR(f30,CNS_Q_FPR+0xF0,r1)
+ SAVE_FPR(f31,CNS_Q_FPR+0xF8,r1)
+
+//switch impure offset from gpr to ipr---
+//orig unfix_impure_gpr r1
+//orig fix_impure_ipr r1
+//orig store_reg1 fpcsr, f0, r1, fpcsr=1
+
+ SAVE_FPR(f0,CNS_Q_FPCSR,r1) // fpcsr loaded above into f0 -- can it reach
+ lda r1, -0x200(r1) // Restore the impure base address
+
+// and back to gpr ---
+//orig unfix_impure_ipr r1
+//orig fix_impure_gpr r1
+
+//orig lda r0, cns_mchksize(r31) // get size of mchk area
+//orig store_reg1 mchkflag, r0, r1, ipr=1
+//orig mb
+
+ lda r1, CNS_Q_IPR(r1) // Point to base of IPR area again
+ // save this using the IPR base (it is closer) not the GRP base as they used...pb
+ lda r0, MACHINE_CHECK_SIZE(r31) // get size of mchk area
+ SAVE_SHADOW(r0,CNS_Q_MCHK,r1);
+ mb
+
+//orig or r31, 1, r0 // get a one
+//orig store_reg1 flag, r0, r1, ipr=1 // set dump area flag
+//orig mb
+
+ lda r1, -CNS_Q_IPR(r1) // back to the base
+ lda r1, 0x200(r1) // Point to center of CPU segment
+ or r31, 1, r0 // get a one
+ SAVE_GPR(r0,CNS_Q_FLAG,r1) // // set dump area valid flag
+ mb
+
+ // restore impure area base
+//orig unfix_impure_gpr r1
+ lda r1, -0x200(r1) // Point to center of CPU segment
+
+ mtpr r31, dtb_ia // clear the dtb
+ mtpr r31, itb_ia // clear the itb
+
+//orig pvc_jsr savsta, bsr=1, dest=1
+ ret r31, (r3) // and back we go
+
+
+
+// .sbttl "PAL_RESTORE_STATE"
+//
+//
+// Pal_restore_state
+//
+//
+// register usage:
+// r1 = addr of impure area
+// r3 = return_address
+// all other regs are scratchable, as they are about to
+// be reloaded from ram.
+//
+// Function:
+// All chip state restored, all SRs, FRs, PTs, IPRs
+// *** except R1, R3, PT0, PT4, PT5 ***
+//
+//
+ ALIGN_BLOCK
+pal_restore_state:
+
+//need to restore sc_ctl,bc_ctl,bc_config??? if so, need to figure out a safe way to do so.
+
+// map the console io area virtually
+ mtpr r31, dtbIa // Clear all DTB entries
+ srl r1, va_s_off, r0 // Clean off byte-within-page offset
+ sll r0, pte_v_pfn, r0 // Shift to form PFN
+ lda r0, pte_m_prot(r0) // Set all read/write enable bits
+ mtpr r0, dtbPte // Load the PTE and set valid
+ mtpr r1, dtbTag // Write the PTE and tag into the DTB
+
+
+// map the next page too, in case impure area crosses page boundary
+ lda r4, (1<<VA_S_OFF)(r1) // Generate address for next page
+ srl r4, va_s_off, r0 // Clean off byte-within-page offset
+ sll r0, pte_v_pfn, r0 // Shift to form PFN
+ lda r0, pte_m_prot(r0) // Set all read/write enable bits
+ mtpr r0, dtbPte // Load the PTE and set valid
+ mtpr r4, dtbTag // Write the PTE and tag into the DTB
+
+// save all floating regs
+ mfpr r0, icsr // Get current ICSR
+ bis zero, 1, r2 // Get a '1'
+ or r2, (1<<(icsr_v_sde-icsr_v_fpe)), r2
+ sll r2, icsr_v_fpe, r2 // Shift bits into position
+ bis r2, r2, r0 // Set ICSR<SDE> and ICSR<FPE>
+ mtpr r0, icsr // Update the chip
+
+ mfpr r31, pt0 // FPE bubble cycle 1 //orig
+ mfpr r31, pt0 // FPE bubble cycle 2 //orig
+ mfpr r31, pt0 // FPE bubble cycle 3 //orig
+
+//orig fix_impure_ipr r1
+//orig restore_reg1 fpcsr, f0, r1, fpcsr=1
+//orig mt_fpcr f0
+//orig
+//orig unfix_impure_ipr r1
+//orig fix_impure_gpr r1 // adjust impure pointer offset for gpr access
+ lda r1, 200(r1) // Point to base of IPR area again
+ RESTORE_FPR(f0,CNS_Q_FPCSR,r1) // can it reach?? pb
+ mt_fpcr f0 // original
+
+ lda r1, 0x200(r1) // point to center of CPU segment
+
+// restore all floating regs
+ RESTORE_FPR(f0,CNS_Q_FPR+0x00,r1)
+ RESTORE_FPR(f1,CNS_Q_FPR+0x08,r1)
+ RESTORE_FPR(f2,CNS_Q_FPR+0x10,r1)
+ RESTORE_FPR(f3,CNS_Q_FPR+0x18,r1)
+ RESTORE_FPR(f4,CNS_Q_FPR+0x20,r1)
+ RESTORE_FPR(f5,CNS_Q_FPR+0x28,r1)
+ RESTORE_FPR(f6,CNS_Q_FPR+0x30,r1)
+ RESTORE_FPR(f7,CNS_Q_FPR+0x38,r1)
+ RESTORE_FPR(f8,CNS_Q_FPR+0x40,r1)
+ RESTORE_FPR(f9,CNS_Q_FPR+0x48,r1)
+ RESTORE_FPR(f10,CNS_Q_FPR+0x50,r1)
+ RESTORE_FPR(f11,CNS_Q_FPR+0x58,r1)
+ RESTORE_FPR(f12,CNS_Q_FPR+0x60,r1)
+ RESTORE_FPR(f13,CNS_Q_FPR+0x68,r1)
+ RESTORE_FPR(f14,CNS_Q_FPR+0x70,r1)
+ RESTORE_FPR(f15,CNS_Q_FPR+0x78,r1)
+ RESTORE_FPR(f16,CNS_Q_FPR+0x80,r1)
+ RESTORE_FPR(f17,CNS_Q_FPR+0x88,r1)
+ RESTORE_FPR(f18,CNS_Q_FPR+0x90,r1)
+ RESTORE_FPR(f19,CNS_Q_FPR+0x98,r1)
+ RESTORE_FPR(f20,CNS_Q_FPR+0xA0,r1)
+ RESTORE_FPR(f21,CNS_Q_FPR+0xA8,r1)
+ RESTORE_FPR(f22,CNS_Q_FPR+0xB0,r1)
+ RESTORE_FPR(f23,CNS_Q_FPR+0xB8,r1)
+ RESTORE_FPR(f24,CNS_Q_FPR+0xC0,r1)
+ RESTORE_FPR(f25,CNS_Q_FPR+0xC8,r1)
+ RESTORE_FPR(f26,CNS_Q_FPR+0xD0,r1)
+ RESTORE_FPR(f27,CNS_Q_FPR+0xD8,r1)
+ RESTORE_FPR(f28,CNS_Q_FPR+0xE0,r1)
+ RESTORE_FPR(f29,CNS_Q_FPR+0xE8,r1)
+ RESTORE_FPR(f30,CNS_Q_FPR+0xF0,r1)
+ RESTORE_FPR(f31,CNS_Q_FPR+0xF8,r1)
+
+// switch impure pointer from gpr to ipr area --
+//orig unfix_impure_gpr r1
+//orig fix_impure_ipr r1
+ lda r1, -0x200(r1) // Restore base address of impure area.
+ lda r1, CNS_Q_IPR(r1) // Point to base of IPR area.
+
+// restore all pal regs
+ RESTORE_IPR(pt0,CNS_Q_PT+0x00,r1) // the osf code didn't save/restore palTemp 0 ?? pboyle
+ RESTORE_IPR(pt1,CNS_Q_PT+0x08,r1)
+ RESTORE_IPR(pt2,CNS_Q_PT+0x10,r1)
+ RESTORE_IPR(pt3,CNS_Q_PT+0x18,r1)
+ RESTORE_IPR(pt4,CNS_Q_PT+0x20,r1)
+ RESTORE_IPR(pt5,CNS_Q_PT+0x28,r1)
+ RESTORE_IPR(pt6,CNS_Q_PT+0x30,r1)
+ RESTORE_IPR(pt7,CNS_Q_PT+0x38,r1)
+ RESTORE_IPR(pt8,CNS_Q_PT+0x40,r1)
+ RESTORE_IPR(pt9,CNS_Q_PT+0x48,r1)
+ RESTORE_IPR(pt10,CNS_Q_PT+0x50,r1)
+ RESTORE_IPR(pt11,CNS_Q_PT+0x58,r1)
+ RESTORE_IPR(pt12,CNS_Q_PT+0x60,r1)
+ RESTORE_IPR(pt13,CNS_Q_PT+0x68,r1)
+ RESTORE_IPR(pt14,CNS_Q_PT+0x70,r1)
+ RESTORE_IPR(pt15,CNS_Q_PT+0x78,r1)
+ RESTORE_IPR(pt16,CNS_Q_PT+0x80,r1)
+ RESTORE_IPR(pt17,CNS_Q_PT+0x88,r1)
+ RESTORE_IPR(pt18,CNS_Q_PT+0x90,r1)
+ RESTORE_IPR(pt19,CNS_Q_PT+0x98,r1)
+ RESTORE_IPR(pt20,CNS_Q_PT+0xA0,r1)
+ RESTORE_IPR(pt21,CNS_Q_PT+0xA8,r1)
+ RESTORE_IPR(pt22,CNS_Q_PT+0xB0,r1)
+ RESTORE_IPR(pt23,CNS_Q_PT+0xB8,r1)
+
+
+//orig restore_reg exc_addr, ipr=1 // restore ipr
+//orig restore_reg pal_base, ipr=1 // restore ipr
+//orig restore_reg ipl, ipr=1 // restore ipr
+//orig restore_reg ps, ipr=1 // restore ipr
+//orig mtpr r0, dtb_cm // set current mode in mbox too
+//orig restore_reg itb_asn, ipr=1
+//orig srl r0, itb_asn_v_asn, r0
+//orig sll r0, dtb_asn_v_asn, r0
+//orig mtpr r0, dtb_asn // set ASN in Mbox too
+//orig restore_reg ivptbr, ipr=1
+//orig mtpr r0, mvptbr // use ivptbr value to restore mvptbr
+//orig restore_reg mcsr, ipr=1
+//orig restore_reg aster, ipr=1
+//orig restore_reg astrr, ipr=1
+//orig restore_reg sirr, ipr=1
+//orig restore_reg maf_mode, ipr=1 // no mbox instruction for 3 cycles
+//orig mfpr r31, pt0 // (may issue with mt maf_mode)
+//orig mfpr r31, pt0 // bubble cycle 1
+//orig mfpr r31, pt0 // bubble cycle 2
+//orig mfpr r31, pt0 // bubble cycle 3
+//orig mfpr r31, pt0 // (may issue with following ld)
+
+ // r0 gets the value of RESTORE_IPR in the macro and this code uses this side effect (gag)
+ RESTORE_IPR(excAddr,CNS_Q_EXC_ADDR,r1)
+ RESTORE_IPR(palBase,CNS_Q_PAL_BASE,r1)
+ RESTORE_IPR(ipl,CNS_Q_IPL,r1)
+ RESTORE_IPR(ips,CNS_Q_IPS,r1)
+ mtpr r0, dtbCm // Set Mbox current mode too.
+ RESTORE_IPR(itbAsn,CNS_Q_ITB_ASN,r1)
+ srl r0, 4, r0
+ sll r0, 57, r0
+ mtpr r0, dtbAsn // Set Mbox ASN too
+ RESTORE_IPR(iVptBr,CNS_Q_IVPTBR,r1)
+ mtpr r0, mVptBr // Set Mbox VptBr too
+ RESTORE_IPR(mcsr,CNS_Q_MCSR,r1)
+ RESTORE_IPR(aster,CNS_Q_ASTER,r1)
+ RESTORE_IPR(astrr,CNS_Q_ASTRR,r1)
+ RESTORE_IPR(sirr,CNS_Q_SIRR,r1)
+ RESTORE_IPR(mafMode,CNS_Q_MAF_MODE,r1)
+ STALL
+ STALL
+ STALL
+ STALL
+ STALL
+
+
+ // restore all integer shadow regs
+ RESTORE_SHADOW( r8,CNS_Q_SHADOW+0x00,r1) // also called p0...p7 in the Hudson code
+ RESTORE_SHADOW( r9,CNS_Q_SHADOW+0x08,r1)
+ RESTORE_SHADOW(r10,CNS_Q_SHADOW+0x10,r1)
+ RESTORE_SHADOW(r11,CNS_Q_SHADOW+0x18,r1)
+ RESTORE_SHADOW(r12,CNS_Q_SHADOW+0x20,r1)
+ RESTORE_SHADOW(r13,CNS_Q_SHADOW+0x28,r1)
+ RESTORE_SHADOW(r14,CNS_Q_SHADOW+0x30,r1)
+ RESTORE_SHADOW(r25,CNS_Q_SHADOW+0x38,r1)
+ RESTORE_IPR(dcMode,CNS_Q_DC_MODE,r1)
+
+ //
+ // Get out of shadow mode
+ //
+
+ mfpr r31, pt0 // pad last load to icsr write (in case of replay, icsr will be written anyway)
+ mfpr r31, pt0 // ""
+ mfpr r0, icsr // Get icsr
+ ldah r2, (1<<(ICSR_V_SDE-16))(r31) // Get a one in SHADOW_ENABLE bit location
+ bic r0, r2, r2 // ICSR with SDE clear
+ mtpr r2, icsr // Turn off SDE - no palshadow rd/wr for 3 bubble cycles
+
+ mfpr r31, pt0 // SDE bubble cycle 1
+ mfpr r31, pt0 // SDE bubble cycle 2
+ mfpr r31, pt0 // SDE bubble cycle 3
+ nop
+
+// switch impure pointer from ipr to gpr area --
+//orig unfix_impure_ipr r1
+//orig fix_impure_gpr r1
+
+// Restore GPRs (r0, r2 are restored later, r1 and r3 are trashed) ...
+
+ lda r1, -CNS_Q_IPR(r1) // Restore base address of impure area
+ lda r1, 0x200(r1) // Point to center of CPU segment
+
+ // restore all integer regs
+ RESTORE_GPR(r4,CNS_Q_GPR+0x20,r1)
+ RESTORE_GPR(r5,CNS_Q_GPR+0x28,r1)
+ RESTORE_GPR(r6,CNS_Q_GPR+0x30,r1)
+ RESTORE_GPR(r7,CNS_Q_GPR+0x38,r1)
+ RESTORE_GPR(r8,CNS_Q_GPR+0x40,r1)
+ RESTORE_GPR(r9,CNS_Q_GPR+0x48,r1)
+ RESTORE_GPR(r10,CNS_Q_GPR+0x50,r1)
+ RESTORE_GPR(r11,CNS_Q_GPR+0x58,r1)
+ RESTORE_GPR(r12,CNS_Q_GPR+0x60,r1)
+ RESTORE_GPR(r13,CNS_Q_GPR+0x68,r1)
+ RESTORE_GPR(r14,CNS_Q_GPR+0x70,r1)
+ RESTORE_GPR(r15,CNS_Q_GPR+0x78,r1)
+ RESTORE_GPR(r16,CNS_Q_GPR+0x80,r1)
+ RESTORE_GPR(r17,CNS_Q_GPR+0x88,r1)
+ RESTORE_GPR(r18,CNS_Q_GPR+0x90,r1)
+ RESTORE_GPR(r19,CNS_Q_GPR+0x98,r1)
+ RESTORE_GPR(r20,CNS_Q_GPR+0xA0,r1)
+ RESTORE_GPR(r21,CNS_Q_GPR+0xA8,r1)
+ RESTORE_GPR(r22,CNS_Q_GPR+0xB0,r1)
+ RESTORE_GPR(r23,CNS_Q_GPR+0xB8,r1)
+ RESTORE_GPR(r24,CNS_Q_GPR+0xC0,r1)
+ RESTORE_GPR(r25,CNS_Q_GPR+0xC8,r1)
+ RESTORE_GPR(r26,CNS_Q_GPR+0xD0,r1)
+ RESTORE_GPR(r27,CNS_Q_GPR+0xD8,r1)
+ RESTORE_GPR(r28,CNS_Q_GPR+0xE0,r1)
+ RESTORE_GPR(r29,CNS_Q_GPR+0xE8,r1)
+ RESTORE_GPR(r30,CNS_Q_GPR+0xF0,r1)
+ RESTORE_GPR(r31,CNS_Q_GPR+0xF8,r1)
+
+//orig // switch impure pointer from gpr to ipr area --
+//orig unfix_impure_gpr r1
+//orig fix_impure_ipr r1
+//orig restore_reg icsr, ipr=1 // restore original icsr- 4 bubbles to hw_rei
+
+ lda t0, -0x200(t0) // Restore base address of impure area.
+ lda t0, CNS_Q_IPR(t0) // Point to base of IPR area again.
+ RESTORE_IPR(icsr,CNS_Q_ICSR,r1)
+
+//orig // and back again --
+//orig unfix_impure_ipr r1
+//orig fix_impure_gpr r1
+//orig store_reg1 flag, r31, r1, ipr=1 // clear dump area valid flag
+//orig mb
+
+ lda t0, -CNS_Q_IPR(t0) // Back to base of impure area again,
+ lda t0, 0x200(t0) // and back to center of CPU segment
+ SAVE_GPR(r31,CNS_Q_FLAG,r1) // Clear the dump area valid flag
+ mb
+
+//orig // and back we go
+//orig// restore_reg 3
+//orig restore_reg 2
+//orig// restore_reg 1
+//orig restore_reg 0
+//orig // restore impure area base
+//orig unfix_impure_gpr r1
+
+ RESTORE_GPR(r2,CNS_Q_GPR+0x10,r1)
+ RESTORE_GPR(r0,CNS_Q_GPR+0x00,r1)
+ lda r1, -0x200(r1) // Restore impure base address
+
+ mfpr r31, pt0 // stall for ldq_p above //orig
+
+ mtpr r31, dtb_ia // clear the tb //orig
+ mtpr r31, itb_ia // clear the itb //orig
+
+//orig pvc_jsr rststa, bsr=1, dest=1
+ ret r31, (r3) // back we go //orig
+
+
+//
+// pal_pal_bug_check -- code has found a bugcheck situation.
+// Set things up and join common machine check flow.
+//
+// Input:
+// r14 - exc_addr
+//
+// On exit:
+// pt0 - saved r0
+// pt1 - saved r1
+// pt4 - saved r4
+// pt5 - saved r5
+// pt6 - saved r6
+// pt10 - saved exc_addr
+// pt_misc<47:32> - mchk code
+// pt_misc<31:16> - scb vector
+// r14 - base of Cbox IPRs in IO space
+// MCES<mchk> is set
+//
+
+ ALIGN_BLOCK
+ .globl pal_pal_bug_check_from_int
+pal_pal_bug_check_from_int:
+ DEBUGSTORE(0x79)
+//simos DEBUG_EXC_ADDR()
+ DEBUGSTORE(0x20)
+//simos bsr r25, put_hex
+ lda r25, mchk_c_bugcheck(r31)
+ addq r25, 1, r25 // set flag indicating we came from interrupt and stack is already pushed
+ br r31, pal_pal_mchk
+ nop
+
+pal_pal_bug_check:
+ lda r25, mchk_c_bugcheck(r31)
+
+pal_pal_mchk:
+ sll r25, 32, r25 // Move mchk code to position
+
+ mtpr r14, pt10 // Stash exc_addr
+ mtpr r14, exc_addr
+
+ mfpr r12, pt_misc // Get MCES and scratch
+ zap r12, 0x3c, r12
+
+ or r12, r25, r12 // Combine mchk code
+ lda r25, scb_v_procmchk(r31) // Get SCB vector
+
+ sll r25, 16, r25 // Move SCBv to position
+ or r12, r25, r25 // Combine SCBv
+
+ mtpr r0, pt0 // Stash for scratch
+ bis r25, mces_m_mchk, r25 // Set MCES<MCHK> bit
+
+ mtpr r25, pt_misc // Save mchk code!scbv!whami!mces
+ ldah r14, 0xfff0(r31)
+
+ mtpr r1, pt1 // Stash for scratch
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+
+ mtpr r4, pt4
+ mtpr r5, pt5
+
+ mtpr r6, pt6
+ blbs r12, sys_double_machine_check // MCHK halt if double machine check
+
+ br r31, sys_mchk_collect_iprs // Join common machine check flow
+
+
+
+// align_to_call_pal_section
+// Align to address of first call_pal entry point - 2000
+
+//
+// HALT - PALcode for HALT instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// GO to console code
+//
+//
+
+ .text 1
+// . = 0x2000
+ CALL_PAL_PRIV(PAL_HALT_ENTRY)
+call_pal_halt:
+ mfpr r31, pt0 // Pad exc_addr read
+ mfpr r31, pt0
+
+ mfpr r12, exc_addr // get PC
+ subq r12, 4, r12 // Point to the HALT
+
+ mtpr r12, exc_addr
+ mtpr r0, pt0
+
+//orig pvc_jsr updpcb, bsr=1
+ bsr r0, pal_update_pcb // update the pcb
+ lda r0, hlt_c_sw_halt(r31) // set halt code to sw halt
+ br r31, sys_enter_console // enter the console
+
+//
+// CFLUSH - PALcode for CFLUSH instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// R16 - contains the PFN of the page to be flushed
+//
+// Function:
+// Flush all Dstream caches of 1 entire page
+// The CFLUSH routine is in the system specific module.
+//
+//
+
+ CALL_PAL_PRIV(PAL_CFLUSH_ENTRY)
+Call_Pal_Cflush:
+ br r31, sys_cflush
+
+//
+// DRAINA - PALcode for DRAINA instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+// Implicit TRAPB performed by hardware.
+//
+// Function:
+// Stall instruction issue until all prior instructions are guaranteed to
+// complete without incurring aborts. For the EV5 implementation, this
+// means waiting until all pending DREADS are returned.
+//
+//
+
+ CALL_PAL_PRIV(PAL_DRAINA_ENTRY)
+Call_Pal_Draina:
+ ldah r14, 0x100(r31) // Init counter. Value?
+ nop
+
+DRAINA_LOOP:
+ subq r14, 1, r14 // Decrement counter
+ mfpr r13, ev5__maf_mode // Fetch status bit
+
+ srl r13, maf_mode_v_dread_pending, r13
+ ble r14, DRAINA_LOOP_TOO_LONG
+
+ nop
+ blbs r13, DRAINA_LOOP // Wait until all DREADS clear
+
+ hw_rei
+
+DRAINA_LOOP_TOO_LONG:
+ br r31, call_pal_halt
+
+// CALL_PAL OPCDECs
+
+ CALL_PAL_PRIV(0x0003)
+CallPal_OpcDec03:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0004)
+CallPal_OpcDec04:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0005)
+CallPal_OpcDec05:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0006)
+CallPal_OpcDec06:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0007)
+CallPal_OpcDec07:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0008)
+CallPal_OpcDec08:
+ br r31, osfpal_calpal_opcdec
+
+//
+// CSERVE - PALcode for CSERVE instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// Various functions for private use of console software
+//
+// option selector in r0
+// arguments in r16....
+// The CSERVE routine is in the system specific module.
+//
+//
+
+ CALL_PAL_PRIV(PAL_CSERVE_ENTRY)
+Call_Pal_Cserve:
+ br r31, sys_cserve
+
+//
+// swppal - PALcode for swppal instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+// Vectored into via hardware PALcode instruction dispatch.
+// R16 contains the new PAL identifier
+// R17:R21 contain implementation-specific entry parameters
+//
+// R0 receives status:
+// 0 success (PAL was switched)
+// 1 unknown PAL variant
+// 2 known PAL variant, but PAL not loaded
+//
+//
+// Function:
+// Swap control to another PAL.
+//
+
+ CALL_PAL_PRIV(PAL_SWPPAL_ENTRY)
+Call_Pal_Swppal:
+ cmpule r16, 255, r0 // see if a kibble was passed
+ cmoveq r16, r16, r0 // if r16=0 then a valid address (ECO 59)
+
+ or r16, r31, r3 // set r3 incase this is a address
+ blbc r0, swppal_cont // nope, try it as an address
+
+ cmpeq r16, 2, r0 // is it our friend OSF?
+ blbc r0, swppal_fail // nope, don't know this fellow
+
+ br r2, CALL_PAL_SWPPAL_10_ // tis our buddy OSF
+
+// .global osfpal_hw_entry_reset
+// .weak osfpal_hw_entry_reset
+// .long <osfpal_hw_entry_reset-pal_start>
+//orig halt // don't know how to get the address here - kludge ok, load pal at 0
+ .long 0 // ?? hack upon hack...pb
+
+CALL_PAL_SWPPAL_10_: ldl_p r3, 0(r2) // fetch target addr
+// ble r3, swppal_fail ; if OSF not linked in say not loaded.
+ mfpr r2, pal_base // fetch pal base
+
+ addq r2, r3, r3 // add pal base
+ lda r2, 0x3FFF(r31) // get pal base checker mask
+
+ and r3, r2, r2 // any funky bits set?
+ cmpeq r2, 0, r0 //
+
+ blbc r0, swppal_fail // return unknown if bad bit set.
+ br r31, swppal_cont
+
+// .sbttl "CALL_PAL OPCDECs"
+
+ CALL_PAL_PRIV(0x000B)
+CallPal_OpcDec0B:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x000C)
+CallPal_OpcDec0C:
+ br r31, osfpal_calpal_opcdec
+
+//
+// wripir - PALcode for wripir instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+// r16 = processor number to interrupt
+//
+// Function:
+// IPIR <- R16
+// Handled in system-specific code
+//
+// Exit:
+// interprocessor interrupt is recorded on the target processor
+// and is initiated when the proper enabling conditions are present.
+//
+
+ CALL_PAL_PRIV(PAL_WRIPIR_ENTRY)
+Call_Pal_Wrpir:
+ br r31, sys_wripir
+
+// .sbttl "CALL_PAL OPCDECs"
+
+ CALL_PAL_PRIV(0x000E)
+CallPal_OpcDec0E:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x000F)
+CallPal_OpcDec0F:
+ br r31, osfpal_calpal_opcdec
+
+//
+// rdmces - PALcode for rdmces instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// R0 <- ZEXT(MCES)
+//
+
+ CALL_PAL_PRIV(PAL_RDMCES_ENTRY)
+Call_Pal_Rdmces:
+ mfpr r0, pt_mces // Read from PALtemp
+ and r0, mces_m_all, r0 // Clear other bits
+
+ hw_rei
+
+//
+// wrmces - PALcode for wrmces instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// If {R16<0> EQ 1} then MCES<0> <- 0 (MCHK)
+// If {R16<1> EQ 1} then MCES<1> <- 0 (SCE)
+// If {R16<2> EQ 1} then MCES<2> <- 0 (PCE)
+// MCES<3> <- R16<3> (DPC)
+// MCES<4> <- R16<4> (DSC)
+//
+//
+
+ CALL_PAL_PRIV(PAL_WRMCES_ENTRY)
+Call_Pal_Wrmces:
+ and r16, ((1<<mces_v_mchk) | (1<<mces_v_sce) | (1<<mces_v_pce)), r13 // Isolate MCHK, SCE, PCE
+ mfpr r14, pt_mces // Get current value
+
+ ornot r31, r13, r13 // Flip all the bits
+ and r16, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r17
+
+ and r14, r13, r1 // Update MCHK, SCE, PCE
+ bic r1, ((1<<mces_v_dpc) | (1<<mces_v_dsc)), r1 // Clear old DPC, DSC
+
+ or r1, r17, r1 // Update DPC and DSC
+ mtpr r1, pt_mces // Write MCES back
+
+ nop // Pad to fix PT write->read restriction
+
+ nop
+ hw_rei
+
+
+
+// CALL_PAL OPCDECs
+
+ CALL_PAL_PRIV(0x0012)
+CallPal_OpcDec12:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0013)
+CallPal_OpcDec13:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0014)
+CallPal_OpcDec14:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0015)
+CallPal_OpcDec15:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0016)
+CallPal_OpcDec16:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0017)
+CallPal_OpcDec17:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0018)
+CallPal_OpcDec18:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0019)
+CallPal_OpcDec19:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x001A)
+CallPal_OpcDec1A:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x001B)
+CallPal_OpcDec1B:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x001C)
+CallPal_OpcDec1C:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x001D)
+CallPal_OpcDec1D:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x001E)
+CallPal_OpcDec1E:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x001F)
+CallPal_OpcDec1F:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0020)
+CallPal_OpcDec20:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0021)
+CallPal_OpcDec21:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0022)
+CallPal_OpcDec22:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0023)
+CallPal_OpcDec23:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0024)
+CallPal_OpcDec24:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0025)
+CallPal_OpcDec25:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0026)
+CallPal_OpcDec26:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0027)
+CallPal_OpcDec27:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0028)
+CallPal_OpcDec28:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x0029)
+CallPal_OpcDec29:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x002A)
+CallPal_OpcDec2A:
+ br r31, osfpal_calpal_opcdec
+
+//
+// wrfen - PALcode for wrfen instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// a0<0> -> ICSR<FPE>
+// Store new FEN in PCB
+// Final value of t0 (r1), t8..t10 (r22..r24) and a0 (r16)
+// are UNPREDICTABLE
+//
+// Issue: What about pending FP loads when FEN goes from on->off????
+//
+
+ CALL_PAL_PRIV(PAL_WRFEN_ENTRY)
+Call_Pal_Wrfen:
+ or r31, 1, r13 // Get a one
+ mfpr r1, ev5__icsr // Get current FPE
+
+ sll r13, icsr_v_fpe, r13 // shift 1 to icsr<fpe> spot, e0
+ and r16, 1, r16 // clean new fen
+
+ sll r16, icsr_v_fpe, r12 // shift new fen to correct bit position
+ bic r1, r13, r1 // zero icsr<fpe>
+
+ or r1, r12, r1 // Or new FEN into ICSR
+ mfpr r12, pt_pcbb // Get PCBB - E1
+
+ mtpr r1, ev5__icsr // write new ICSR. 3 Bubble cycles to HW_REI
+ stl_p r16, osfpcb_q_fen(r12) // Store FEN in PCB.
+
+ mfpr r31, pt0 // Pad ICSR<FPE> write.
+ mfpr r31, pt0
+
+ mfpr r31, pt0
+// pvc_violate 225 // cuz PVC can't distinguish which bits changed
+ hw_rei
+
+
+ CALL_PAL_PRIV(0x002C)
+CallPal_OpcDec2C:
+ br r31, osfpal_calpal_opcdec
+
+//
+// wrvptpr - PALcode for wrvptpr instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// vptptr <- a0 (r16)
+//
+
+ CALL_PAL_PRIV(PAL_WRVPTPTR_ENTRY)
+Call_Pal_Wrvptptr:
+ mtpr r16, ev5__mvptbr // Load Mbox copy
+ mtpr r16, ev5__ivptbr // Load Ibox copy
+ nop // Pad IPR write
+ nop
+ hw_rei
+
+ CALL_PAL_PRIV(0x002E)
+CallPal_OpcDec2E:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_PRIV(0x002F)
+CallPal_OpcDec2F:
+ br r31, osfpal_calpal_opcdec
+
+
+//
+// swpctx - PALcode for swpctx instruction
+//
+// Entry:
+// hardware dispatch via callPal instruction
+// R16 -> new pcb
+//
+// Function:
+// dynamic state moved to old pcb
+// new state loaded from new pcb
+// pcbb pointer set
+// old pcbb returned in R0
+//
+// Note: need to add perf monitor stuff
+//
+
+ CALL_PAL_PRIV(PAL_SWPCTX_ENTRY)
+Call_Pal_Swpctx:
+ rpcc r13 // get cyccounter
+ mfpr r0, pt_pcbb // get pcbb
+
+ ldq_p r22, osfpcb_q_fen(r16) // get new fen/pme
+ ldq_p r23, osfpcb_l_cc(r16) // get new asn
+
+ srl r13, 32, r25 // move offset
+ mfpr r24, pt_usp // get usp
+
+ stq_p r30, osfpcb_q_ksp(r0) // store old ksp
+// pvc_violate 379 // stq_p can't trap except replay. only problem if mf same ipr in same shadow.
+ mtpr r16, pt_pcbb // set new pcbb
+
+ stq_p r24, osfpcb_q_usp(r0) // store usp
+ addl r13, r25, r25 // merge for new time
+
+ stl_p r25, osfpcb_l_cc(r0) // save time
+ ldah r24, (1<<(icsr_v_fpe-16))(r31)
+
+ and r22, 1, r12 // isolate fen
+ mfpr r25, icsr // get current icsr
+
+ lda r24, (1<<icsr_v_pmp)(r24)
+ br r31, swpctx_cont
+
+//
+// wrval - PALcode for wrval instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// sysvalue <- a0 (r16)
+//
+
+ CALL_PAL_PRIV(PAL_WRVAL_ENTRY)
+Call_Pal_Wrval:
+ nop
+ mtpr r16, pt_sysval // Pad paltemp write
+ nop
+ nop
+ hw_rei
+
+//
+// rdval - PALcode for rdval instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// v0 (r0) <- sysvalue
+//
+
+ CALL_PAL_PRIV(PAL_RDVAL_ENTRY)
+Call_Pal_Rdval:
+ nop
+ mfpr r0, pt_sysval
+ nop
+ hw_rei
+
+//
+// tbi - PALcode for tbi instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// TB invalidate
+// r16/a0 = TBI type
+// r17/a1 = Va for TBISx instructions
+//
+
+ CALL_PAL_PRIV(PAL_TBI_ENTRY)
+Call_Pal_Tbi:
+ addq r16, 2, r16 // change range to 0-2
+ br r23, CALL_PAL_tbi_10_ // get our address
+
+CALL_PAL_tbi_10_: cmpult r16, 6, r22 // see if in range
+ lda r23, tbi_tbl-CALL_PAL_tbi_10_(r23) // set base to start of table
+ sll r16, 4, r16 // * 16
+ blbc r22, CALL_PAL_tbi_30_ // go rei, if not
+
+ addq r23, r16, r23 // addr of our code
+//orig pvc_jsr tbi
+ jmp r31, (r23) // and go do it
+
+CALL_PAL_tbi_30_:
+ hw_rei
+ nop
+
+//
+// wrent - PALcode for wrent instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// Update ent* in paltemps
+// r16/a0 = Address of entry routine
+// r17/a1 = Entry Number 0..5
+//
+// r22, r23 trashed
+//
+
+ CALL_PAL_PRIV(PAL_WRENT_ENTRY)
+Call_Pal_Wrent:
+ cmpult r17, 6, r22 // see if in range
+ br r23, CALL_PAL_wrent_10_ // get our address
+
+CALL_PAL_wrent_10_: bic r16, 3, r16 // clean pc
+ blbc r22, CALL_PAL_wrent_30_ // go rei, if not in range
+
+ lda r23, wrent_tbl-CALL_PAL_wrent_10_(r23) // set base to start of table
+ sll r17, 4, r17 // *16
+
+ addq r17, r23, r23 // Get address in table
+//orig pvc_jsr wrent
+ jmp r31, (r23) // and go do it
+
+CALL_PAL_wrent_30_:
+ hw_rei // out of range, just return
+
+//
+// swpipl - PALcode for swpipl instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// v0 (r0) <- PS<IPL>
+// PS<IPL> <- a0<2:0> (r16)
+//
+// t8 (r22) is scratch
+//
+
+ CALL_PAL_PRIV(PAL_SWPIPL_ENTRY)
+Call_Pal_Swpipl:
+ and r16, osfps_m_ipl, r16 // clean New ipl
+ mfpr r22, pt_intmask // get int mask
+
+ extbl r22, r16, r22 // get mask for this ipl
+ bis r11, r31, r0 // return old ipl
+
+ bis r16, r31, r11 // set new ps
+ mtpr r22, ev5__ipl // set new mask
+
+ mfpr r31, pt0 // pad ipl write
+ mfpr r31, pt0 // pad ipl write
+
+ hw_rei // back
+
+//
+// rdps - PALcode for rdps instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// v0 (r0) <- ps
+//
+
+ CALL_PAL_PRIV(PAL_RDPS_ENTRY)
+Call_Pal_Rdps:
+ bis r11, r31, r0 // Fetch PALshadow PS
+ nop // Must be 2 cycles long
+ hw_rei
+
+//
+// wrkgp - PALcode for wrkgp instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// kgp <- a0 (r16)
+//
+
+ CALL_PAL_PRIV(PAL_WRKGP_ENTRY)
+Call_Pal_Wrkgp:
+ nop
+ mtpr r16, pt_kgp
+ nop // Pad for pt write->read restriction
+ nop
+ hw_rei
+
+//
+// wrusp - PALcode for wrusp instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// usp <- a0 (r16)
+//
+
+ CALL_PAL_PRIV(PAL_WRUSP_ENTRY)
+Call_Pal_Wrusp:
+ nop
+ mtpr r16, pt_usp
+ nop // Pad possible pt write->read restriction
+ nop
+ hw_rei
+
+//
+// wrperfmon - PALcode for wrperfmon instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+//
+// Function:
+// Various control functions for the onchip performance counters
+//
+// option selector in r16
+// option argument in r17
+// returned status in r0
+//
+//
+// r16 = 0 Disable performance monitoring for one or more cpu's
+// r17 = 0 disable no counters
+// r17 = bitmask disable counters specified in bit mask (1=disable)
+//
+// r16 = 1 Enable performance monitoring for one or more cpu's
+// r17 = 0 enable no counters
+// r17 = bitmask enable counters specified in bit mask (1=enable)
+//
+// r16 = 2 Mux select for one or more cpu's
+// r17 = Mux selection (cpu specific)
+// <24:19> bc_ctl<pm_mux_sel> field (see spec)
+// <31>,<7:4>,<3:0> pmctr <sel0>,<sel1>,<sel2> fields (see spec)
+//
+// r16 = 3 Options
+// r17 = (cpu specific)
+// <0> = 0 log all processes
+// <0> = 1 log only selected processes
+// <30,9,8> mode select - ku,kp,kk
+//
+// r16 = 4 Interrupt frequency select
+// r17 = (cpu specific) indicates interrupt frequencies desired for each
+// counter, with "zero interrupts" being an option
+// frequency info in r17 bits as defined by PMCTR_CTL<FRQx> below
+//
+// r16 = 5 Read Counters
+// r17 = na
+// r0 = value (same format as ev5 pmctr)
+// <0> = 0 Read failed
+// <0> = 1 Read succeeded
+//
+// r16 = 6 Write Counters
+// r17 = value (same format as ev5 pmctr; all counters written simultaneously)
+//
+// r16 = 7 Enable performance monitoring for one or more cpu's and reset counter to 0
+// r17 = 0 enable no counters
+// r17 = bitmask enable & clear counters specified in bit mask (1=enable & clear)
+//
+//=============================================================================
+//Assumptions:
+//PMCTR_CTL:
+//
+// <15:14> CTL0 -- encoded frequency select and enable - CTR0
+// <13:12> CTL1 -- " - CTR1
+// <11:10> CTL2 -- " - CTR2
+//
+// <9:8> FRQ0 -- frequency select for CTR0 (no enable info)
+// <7:6> FRQ1 -- frequency select for CTR1
+// <5:4> FRQ2 -- frequency select for CTR2
+//
+// <0> all vs. select processes (0=all,1=select)
+//
+// where
+// FRQx<1:0>
+// 0 1 disable interrupt
+// 1 0 frequency = 65536 (16384 for ctr2)
+// 1 1 frequency = 256
+// note: FRQx<1:0> = 00 will keep counters from ever being enabled.
+//
+//=============================================================================
+//
+ CALL_PAL_PRIV(0x0039)
+// unsupported in Hudson code .. pboyle Nov/95
+CALL_PAL_Wrperfmon:
+ // "real" performance monitoring code
+ cmpeq r16, 1, r0 // check for enable
+ bne r0, perfmon_en // br if requested to enable
+
+ cmpeq r16, 2, r0 // check for mux ctl
+ bne r0, perfmon_muxctl // br if request to set mux controls
+
+ cmpeq r16, 3, r0 // check for options
+ bne r0, perfmon_ctl // br if request to set options
+
+ cmpeq r16, 4, r0 // check for interrupt frequency select
+ bne r0, perfmon_freq // br if request to change frequency select
+
+ cmpeq r16, 5, r0 // check for counter read request
+ bne r0, perfmon_rd // br if request to read counters
+
+ cmpeq r16, 6, r0 // check for counter write request
+ bne r0, perfmon_wr // br if request to write counters
+
+ cmpeq r16, 7, r0 // check for counter clear/enable request
+ bne r0, perfmon_enclr // br if request to clear/enable counters
+
+ beq r16, perfmon_dis // br if requested to disable (r16=0)
+ br r31, perfmon_unknown // br if unknown request
+
+//
+// rdusp - PALcode for rdusp instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// v0 (r0) <- usp
+//
+
+ CALL_PAL_PRIV(PAL_RDUSP_ENTRY)
+Call_Pal_Rdusp:
+ nop
+ mfpr r0, pt_usp
+ hw_rei
+
+
+ CALL_PAL_PRIV(0x003B)
+CallPal_OpcDec3B:
+ br r31, osfpal_calpal_opcdec
+
+//
+// whami - PALcode for whami instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// v0 (r0) <- whami
+//
+ CALL_PAL_PRIV(PAL_WHAMI_ENTRY)
+Call_Pal_Whami:
+ nop
+ mfpr r0, pt_whami // Get Whami
+ extbl r0, 1, r0 // Isolate just whami bits
+ hw_rei
+
+//
+// retsys - PALcode for retsys instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+// 00(sp) contains return pc
+// 08(sp) contains r29
+//
+// Function:
+// Return from system call.
+// mode switched from kern to user.
+// stacks swapped, ugp, upc restored.
+// r23, r25 junked
+//
+
+ CALL_PAL_PRIV(PAL_RETSYS_ENTRY)
+Call_Pal_Retsys:
+ lda r25, osfsf_c_size(sp) // pop stack
+ bis r25, r31, r14 // touch r25 & r14 to stall mf exc_addr
+
+ mfpr r14, exc_addr // save exc_addr in case of fault
+ ldq r23, osfsf_pc(sp) // get pc
+
+ ldq r29, osfsf_gp(sp) // get gp
+ stl_c r31, -4(sp) // clear lock_flag
+
+ lda r11, 1<<osfps_v_mode(r31)// new PS:mode=user
+ mfpr r30, pt_usp // get users stack
+
+ bic r23, 3, r23 // clean return pc
+ mtpr r31, ev5__ipl // zero ibox IPL - 2 bubbles to hw_rei
+
+ mtpr r11, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
+ mtpr r11, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
+
+ mtpr r23, exc_addr // set return address - 1 bubble to hw_rei
+ mtpr r25, pt_ksp // save kern stack
+
+ rc r31 // clear inter_flag
+// pvc_violate 248 // possible hidden mt->mf pt violation ok in callpal
+ hw_rei_spe // and back
+
+
+ CALL_PAL_PRIV(0x003E)
+CallPal_OpcDec3E:
+ br r31, osfpal_calpal_opcdec
+
+//
+// rti - PALcode for rti instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// 00(sp) -> ps
+// 08(sp) -> pc
+// 16(sp) -> r29 (gp)
+// 24(sp) -> r16 (a0)
+// 32(sp) -> r17 (a1)
+// 40(sp) -> r18 (a3)
+//
+
+ CALL_PAL_PRIV(PAL_RTI_ENTRY)
+ /* called once by platform_tlaser */
+ .globl Call_Pal_Rti
+Call_Pal_Rti:
+ lda r25, osfsf_c_size(sp) // get updated sp
+ bis r25, r31, r14 // touch r14,r25 to stall mf exc_addr
+
+ mfpr r14, exc_addr // save PC in case of fault
+ rc r31 // clear intr_flag
+
+ ldq r12, -6*8(r25) // get ps
+ ldq r13, -5*8(r25) // pc
+
+ ldq r18, -1*8(r25) // a2
+ ldq r17, -2*8(r25) // a1
+
+ ldq r16, -3*8(r25) // a0
+ ldq r29, -4*8(r25) // gp
+
+ bic r13, 3, r13 // clean return pc
+ stl_c r31, -4(r25) // clear lock_flag
+
+ and r12, osfps_m_mode, r11 // get mode
+ mtpr r13, exc_addr // set return address
+
+ beq r11, rti_to_kern // br if rti to Kern
+ br r31, rti_to_user // out of call_pal space
+
+
+///////////////////////////////////////////////////
+// Start the Unprivileged CALL_PAL Entry Points
+///////////////////////////////////////////////////
+
+//
+// bpt - PALcode for bpt instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// Build stack frame
+// a0 <- code
+// a1 <- unpred
+// a2 <- unpred
+// vector via entIF
+//
+//
+//
+ .text 1
+// . = 0x3000
+ CALL_PAL_UNPRIV(PAL_BPT_ENTRY)
+Call_Pal_Bpt:
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ bis r11, r31, r12 // Save PS for stack write
+ bge r25, CALL_PAL_bpt_10_ // no stack swap needed if cm=kern
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r11 // Set new PS
+ mfpr r30, pt_ksp
+
+CALL_PAL_bpt_10_:
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+ mfpr r14, exc_addr // get pc
+
+ stq r16, osfsf_a0(sp) // save regs
+ bis r31, osf_a0_bpt, r16 // set a0
+
+ stq r17, osfsf_a1(sp) // a1
+ br r31, bpt_bchk_common // out of call_pal space
+
+
+//
+// bugchk - PALcode for bugchk instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// Build stack frame
+// a0 <- code
+// a1 <- unpred
+// a2 <- unpred
+// vector via entIF
+//
+//
+//
+ CALL_PAL_UNPRIV(PAL_BUGCHK_ENTRY)
+Call_Pal_Bugchk:
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ bis r11, r31, r12 // Save PS for stack write
+ bge r25, CALL_PAL_bugchk_10_ // no stack swap needed if cm=kern
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r11 // Set new PS
+ mfpr r30, pt_ksp
+
+CALL_PAL_bugchk_10_:
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+ mfpr r14, exc_addr // get pc
+
+ stq r16, osfsf_a0(sp) // save regs
+ bis r31, osf_a0_bugchk, r16 // set a0
+
+ stq r17, osfsf_a1(sp) // a1
+ br r31, bpt_bchk_common // out of call_pal space
+
+
+ CALL_PAL_UNPRIV(0x0082)
+CallPal_OpcDec82:
+ br r31, osfpal_calpal_opcdec
+
+//
+// callsys - PALcode for callsys instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// Switch mode to kernel and build a callsys stack frame.
+// sp = ksp
+// gp = kgp
+// t8 - t10 (r22-r24) trashed
+//
+//
+//
+ CALL_PAL_UNPRIV(PAL_CALLSYS_ENTRY)
+Call_Pal_Callsys:
+
+ and r11, osfps_m_mode, r24 // get mode
+ mfpr r22, pt_ksp // get ksp
+
+ beq r24, sys_from_kern // sysCall from kern is not allowed
+ mfpr r12, pt_entsys // get address of callSys routine
+
+//
+// from here on we know we are in user going to Kern
+//
+ mtpr r31, ev5__dtb_cm // set Mbox current mode - no virt ref for 2 cycles
+ mtpr r31, ev5__ps // set Ibox current mode - 2 bubble to hw_rei
+
+ bis r31, r31, r11 // PS=0 (mode=kern)
+ mfpr r23, exc_addr // get pc
+
+ mtpr r30, pt_usp // save usp
+ lda sp, 0-osfsf_c_size(r22)// set new sp
+
+ stq r29, osfsf_gp(sp) // save user gp/r29
+ stq r24, osfsf_ps(sp) // save ps
+
+ stq r23, osfsf_pc(sp) // save pc
+ mtpr r12, exc_addr // set address
+ // 1 cycle to hw_rei
+
+ mfpr r29, pt_kgp // get the kern gp/r29
+
+ hw_rei_spe // and off we go!
+
+
+ CALL_PAL_UNPRIV(0x0084)
+CallPal_OpcDec84:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0085)
+CallPal_OpcDec85:
+ br r31, osfpal_calpal_opcdec
+
+//
+// imb - PALcode for imb instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// Flush the writebuffer and flush the Icache
+//
+//
+//
+ CALL_PAL_UNPRIV(PAL_IMB_ENTRY)
+Call_Pal_Imb:
+ mb // Clear the writebuffer
+ mfpr r31, ev5__mcsr // Sync with clear
+ nop
+ nop
+ br r31, pal_ic_flush // Flush Icache
+
+
+// CALL_PAL OPCDECs
+
+ CALL_PAL_UNPRIV(0x0087)
+CallPal_OpcDec87:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0088)
+CallPal_OpcDec88:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0089)
+CallPal_OpcDec89:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x008A)
+CallPal_OpcDec8A:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x008B)
+CallPal_OpcDec8B:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x008C)
+CallPal_OpcDec8C:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x008D)
+CallPal_OpcDec8D:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x008E)
+CallPal_OpcDec8E:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x008F)
+CallPal_OpcDec8F:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0090)
+CallPal_OpcDec90:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0091)
+CallPal_OpcDec91:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0092)
+CallPal_OpcDec92:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0093)
+CallPal_OpcDec93:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0094)
+CallPal_OpcDec94:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0095)
+CallPal_OpcDec95:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0096)
+CallPal_OpcDec96:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0097)
+CallPal_OpcDec97:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0098)
+CallPal_OpcDec98:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x0099)
+CallPal_OpcDec99:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x009A)
+CallPal_OpcDec9A:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x009B)
+CallPal_OpcDec9B:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x009C)
+CallPal_OpcDec9C:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x009D)
+CallPal_OpcDec9D:
+ br r31, osfpal_calpal_opcdec
+
+//
+// rdunique - PALcode for rdunique instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// v0 (r0) <- unique
+//
+//
+//
+ CALL_PAL_UNPRIV(PAL_RDUNIQUE_ENTRY)
+CALL_PALrdunique_:
+ mfpr r0, pt_pcbb // get pcb pointer
+ ldq_p r0, osfpcb_q_unique(r0) // get new value
+
+ hw_rei
+
+//
+// wrunique - PALcode for wrunique instruction
+//
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// unique <- a0 (r16)
+//
+//
+//
+CALL_PAL_UNPRIV(PAL_WRUNIQUE_ENTRY)
+CALL_PAL_Wrunique:
+ nop
+ mfpr r12, pt_pcbb // get pcb pointer
+ stq_p r16, osfpcb_q_unique(r12)// get new value
+ nop // Pad palshadow write
+ hw_rei // back
+
+// CALL_PAL OPCDECs
+
+ CALL_PAL_UNPRIV(0x00A0)
+CallPal_OpcDecA0:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00A1)
+CallPal_OpcDecA1:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00A2)
+CallPal_OpcDecA2:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00A3)
+CallPal_OpcDecA3:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00A4)
+CallPal_OpcDecA4:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00A5)
+CallPal_OpcDecA5:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00A6)
+CallPal_OpcDecA6:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00A7)
+CallPal_OpcDecA7:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00A8)
+CallPal_OpcDecA8:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00A9)
+CallPal_OpcDecA9:
+ br r31, osfpal_calpal_opcdec
+
+
+//
+// gentrap - PALcode for gentrap instruction
+//
+// CALL_PAL_gentrap:
+// Entry:
+// Vectored into via hardware PALcode instruction dispatch.
+//
+// Function:
+// Build stack frame
+// a0 <- code
+// a1 <- unpred
+// a2 <- unpred
+// vector via entIF
+//
+//
+
+ CALL_PAL_UNPRIV(0x00AA)
+// unsupported in Hudson code .. pboyle Nov/95
+CALL_PAL_gentrap:
+ sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ bis r11, r31, r12 // Save PS for stack write
+ bge r25, CALL_PAL_gentrap_10_ // no stack swap needed if cm=kern
+
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel -
+ // no virt ref for next 2 cycles
+ mtpr r30, pt_usp // save user stack
+
+ bis r31, r31, r11 // Set new PS
+ mfpr r30, pt_ksp
+
+CALL_PAL_gentrap_10_:
+ lda sp, 0-osfsf_c_size(sp)// allocate stack space
+ mfpr r14, exc_addr // get pc
+
+ stq r16, osfsf_a0(sp) // save regs
+ bis r31, osf_a0_gentrap, r16// set a0
+
+ stq r17, osfsf_a1(sp) // a1
+ br r31, bpt_bchk_common // out of call_pal space
+
+
+// CALL_PAL OPCDECs
+
+ CALL_PAL_UNPRIV(0x00AB)
+CallPal_OpcDecAB:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00AC)
+CallPal_OpcDecAC:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00AD)
+CallPal_OpcDecAD:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00AE)
+CallPal_OpcDecAE:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00AF)
+CallPal_OpcDecAF:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B0)
+CallPal_OpcDecB0:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B1)
+CallPal_OpcDecB1:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B2)
+CallPal_OpcDecB2:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B3)
+CallPal_OpcDecB3:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B4)
+CallPal_OpcDecB4:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B5)
+CallPal_OpcDecB5:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B6)
+CallPal_OpcDecB6:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B7)
+CallPal_OpcDecB7:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B8)
+CallPal_OpcDecB8:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00B9)
+CallPal_OpcDecB9:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00BA)
+CallPal_OpcDecBA:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00BB)
+CallPal_OpcDecBB:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00BC)
+CallPal_OpcDecBC:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00BD)
+CallPal_OpcDecBD:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00BE)
+CallPal_OpcDecBE:
+ br r31, osfpal_calpal_opcdec
+
+ CALL_PAL_UNPRIV(0x00BF)
+CallPal_OpcDecBF:
+ // MODIFIED BY EGH 2/25/04
+ br r31, copypal_impl
+
+
+/*======================================================================*/
+/* OSF/1 CALL_PAL CONTINUATION AREA */
+/*======================================================================*/
+
+ .text 2
+
+ . = 0x4000
+
+
+// Continuation of MTPR_PERFMON
+ ALIGN_BLOCK
+ // "real" performance monitoring code
+// mux ctl
+perfmon_muxctl:
+ lda r8, 1(r31) // get a 1
+ sll r8, pmctr_v_sel0, r8 // move to sel0 position
+ or r8, ((0xf<<pmctr_v_sel1) | (0xf<<pmctr_v_sel2)), r8 // build mux select mask
+ and r17, r8, r25 // isolate pmctr mux select bits
+ mfpr r0, ev5__pmctr
+ bic r0, r8, r0 // clear old mux select bits
+ or r0,r25, r25 // or in new mux select bits
+ mtpr r25, ev5__pmctr
+
+ // ok, now tackle cbox mux selects
+ ldah r14, 0xfff0(r31)
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+//orig get_bc_ctl_shadow r16 // bc_ctl returned in lower longword
+// adapted from ev5_pal_macros.mar
+ mfpr r16, pt_impure
+ lda r16, CNS_Q_IPR(r16)
+ RESTORE_SHADOW(r16,CNS_Q_BC_CTL,r16);
+
+ lda r8, 0x3F(r31) // build mux select mask
+ sll r8, bc_ctl_v_pm_mux_sel, r8
+
+ and r17, r8, r25 // isolate bc_ctl mux select bits
+ bic r16, r8, r16 // isolate old mux select bits
+ or r16, r25, r25 // create new bc_ctl
+ mb // clear out cbox for future ipr write
+ stq_p r25, ev5__bc_ctl(r14) // store to cbox ipr
+ mb // clear out cbox for future ipr write
+
+//orig update_bc_ctl_shadow r25, r16 // r25=value, r16-overwritten with adjusted impure ptr
+// adapted from ev5_pal_macros.mar
+ mfpr r16, pt_impure
+ lda r16, CNS_Q_IPR(r16)
+ SAVE_SHADOW(r25,CNS_Q_BC_CTL,r16);
+
+ br r31, perfmon_success
+
+
+// requested to disable perf monitoring
+perfmon_dis:
+ mfpr r14, ev5__pmctr // read ibox pmctr ipr
+perfmon_dis_ctr0: // and begin with ctr0
+ blbc r17, perfmon_dis_ctr1 // do not disable ctr0
+ lda r8, 3(r31)
+ sll r8, pmctr_v_ctl0, r8
+ bic r14, r8, r14 // disable ctr0
+perfmon_dis_ctr1:
+ srl r17, 1, r17
+ blbc r17, perfmon_dis_ctr2 // do not disable ctr1
+ lda r8, 3(r31)
+ sll r8, pmctr_v_ctl1, r8
+ bic r14, r8, r14 // disable ctr1
+perfmon_dis_ctr2:
+ srl r17, 1, r17
+ blbc r17, perfmon_dis_update // do not disable ctr2
+ lda r8, 3(r31)
+ sll r8, pmctr_v_ctl2, r8
+ bic r14, r8, r14 // disable ctr2
+perfmon_dis_update:
+ mtpr r14, ev5__pmctr // update pmctr ipr
+//;the following code is not needed for ev5 pass2 and later, but doesn't hurt anything to leave in
+// adapted from ev5_pal_macros.mar
+//orig get_pmctr_ctl r8, r25 // pmctr_ctl bit in r8. adjusted impure pointer in r25
+ mfpr r25, pt_impure
+ lda r25, CNS_Q_IPR(r25)
+ RESTORE_SHADOW(r8,CNS_Q_PM_CTL,r25);
+
+ lda r17, 0x3F(r31) // build mask
+ sll r17, pmctr_v_ctl2, r17 // shift mask to correct position
+ and r14, r17, r14 // isolate ctl bits
+ bic r8, r17, r8 // clear out old ctl bits
+ or r14, r8, r14 // create shadow ctl bits
+//orig store_reg1 pmctr_ctl, r14, r25, ipr=1 // update pmctr_ctl register
+//adjusted impure pointer still in r25
+ SAVE_SHADOW(r14,CNS_Q_PM_CTL,r25);
+
+ br r31, perfmon_success
+
+
+// requested to enable perf monitoring
+//;the following code can be greatly simplified for pass2, but should work fine as is.
+
+
+perfmon_enclr:
+ lda r9, 1(r31) // set enclr flag
+ br perfmon_en_cont
+
+perfmon_en:
+ bis r31, r31, r9 // clear enclr flag
+
+perfmon_en_cont:
+ mfpr r8, pt_pcbb // get PCB base
+//orig get_pmctr_ctl r25, r25
+ mfpr r25, pt_impure
+ lda r25, CNS_Q_IPR(r25)
+ RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r25);
+
+ ldq_p r16, osfpcb_q_fen(r8) // read DAT/PME/FEN quadword
+ mfpr r14, ev5__pmctr // read ibox pmctr ipr
+ srl r16, osfpcb_v_pme, r16 // get pme bit
+ mfpr r13, icsr
+ and r16, 1, r16 // isolate pme bit
+
+ // this code only needed in pass2 and later
+ lda r12, 1<<icsr_v_pmp(r31) // pb
+ bic r13, r12, r13 // clear pmp bit
+ sll r16, icsr_v_pmp, r12 // move pme bit to icsr<pmp> position
+ or r12, r13, r13 // new icsr with icsr<pmp> bit set/clear
+ mtpr r13, icsr // update icsr
+
+ bis r31, 1, r16 // set r16<0> on pass2 to update pmctr always (icsr provides real enable)
+
+ sll r25, 6, r25 // shift frequency bits into pmctr_v_ctl positions
+ bis r14, r31, r13 // copy pmctr
+
+perfmon_en_ctr0: // and begin with ctr0
+ blbc r17, perfmon_en_ctr1 // do not enable ctr0
+
+ blbc r9, perfmon_en_noclr0 // enclr flag set, clear ctr0 field
+ lda r8, 0xffff(r31)
+ zapnot r8, 3, r8 // ctr0<15:0> mask
+ sll r8, pmctr_v_ctr0, r8
+ bic r14, r8, r14 // clear ctr bits
+ bic r13, r8, r13 // clear ctr bits
+
+perfmon_en_noclr0:
+//orig get_addr r8, 3<<pmctr_v_ctl0, r31
+ LDLI(r8, (3<<pmctr_v_ctl0))
+ and r25, r8, r12 //isolate frequency select bits for ctr0
+ bic r14, r8, r14 // clear ctl0 bits in preparation for enabling
+ or r14,r12,r14 // or in new ctl0 bits
+
+perfmon_en_ctr1: // enable ctr1
+ srl r17, 1, r17 // get ctr1 enable
+ blbc r17, perfmon_en_ctr2 // do not enable ctr1
+
+ blbc r9, perfmon_en_noclr1 // if enclr flag set, clear ctr1 field
+ lda r8, 0xffff(r31)
+ zapnot r8, 3, r8 // ctr1<15:0> mask
+ sll r8, pmctr_v_ctr1, r8
+ bic r14, r8, r14 // clear ctr bits
+ bic r13, r8, r13 // clear ctr bits
+
+perfmon_en_noclr1:
+//orig get_addr r8, 3<<pmctr_v_ctl1, r31
+ LDLI(r8, (3<<pmctr_v_ctl1))
+ and r25, r8, r12 //isolate frequency select bits for ctr1
+ bic r14, r8, r14 // clear ctl1 bits in preparation for enabling
+ or r14,r12,r14 // or in new ctl1 bits
+
+perfmon_en_ctr2: // enable ctr2
+ srl r17, 1, r17 // get ctr2 enable
+ blbc r17, perfmon_en_return // do not enable ctr2 - return
+
+ blbc r9, perfmon_en_noclr2 // if enclr flag set, clear ctr2 field
+ lda r8, 0x3FFF(r31) // ctr2<13:0> mask
+ sll r8, pmctr_v_ctr2, r8
+ bic r14, r8, r14 // clear ctr bits
+ bic r13, r8, r13 // clear ctr bits
+
+perfmon_en_noclr2:
+//orig get_addr r8, 3<<pmctr_v_ctl2, r31
+ LDLI(r8, (3<<pmctr_v_ctl2))
+ and r25, r8, r12 //isolate frequency select bits for ctr2
+ bic r14, r8, r14 // clear ctl2 bits in preparation for enabling
+ or r14,r12,r14 // or in new ctl2 bits
+
+perfmon_en_return:
+ cmovlbs r16, r14, r13 // if pme enabled, move enables into pmctr
+ // else only do the counter clears
+ mtpr r13, ev5__pmctr // update pmctr ipr
+
+//;this code not needed for pass2 and later, but does not hurt to leave it in
+ lda r8, 0x3F(r31)
+//orig get_pmctr_ctl r25, r12 // read pmctr ctl; r12=adjusted impure pointer
+ mfpr r12, pt_impure
+ lda r12, CNS_Q_IPR(r12)
+ RESTORE_SHADOW(r25,CNS_Q_PM_CTL,r12);
+
+ sll r8, pmctr_v_ctl2, r8 // build ctl mask
+ and r8, r14, r14 // isolate new ctl bits
+ bic r25, r8, r25 // clear out old ctl value
+ or r25, r14, r14 // create new pmctr_ctl
+//orig store_reg1 pmctr_ctl, r14, r12, ipr=1
+ SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr
+
+ br r31, perfmon_success
+
+
+// options...
+perfmon_ctl:
+
+// set mode
+//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer
+ mfpr r12, pt_impure
+ lda r12, CNS_Q_IPR(r12)
+ RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12);
+
+ // build mode mask for pmctr register
+ LDLI(r8, ((1<<pmctr_v_killu) | (1<<pmctr_v_killp) | (1<<pmctr_v_killk)))
+ mfpr r0, ev5__pmctr
+ and r17, r8, r25 // isolate pmctr mode bits
+ bic r0, r8, r0 // clear old mode bits
+ or r0, r25, r25 // or in new mode bits
+ mtpr r25, ev5__pmctr
+
+ // the following code will only be used in pass2, but should
+ // not hurt anything if run in pass1.
+ mfpr r8, icsr
+ lda r25, 1<<icsr_v_pma(r31) // set icsr<pma> if r17<0>=0
+ bic r8, r25, r8 // clear old pma bit
+ cmovlbs r17, r31, r25 // and clear icsr<pma> if r17<0>=1
+ or r8, r25, r8
+ mtpr r8, icsr // 4 bubbles to hw_rei
+ mfpr r31, pt0 // pad icsr write
+ mfpr r31, pt0 // pad icsr write
+
+ // the following code not needed for pass2 and later, but
+ // should work anyway.
+ bis r14, 1, r14 // set for select processes
+ blbs r17, perfmon_sp // branch if select processes
+ bic r14, 1, r14 // all processes
+perfmon_sp:
+//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register
+ SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr
+ br r31, perfmon_success
+
+// counter frequency select
+perfmon_freq:
+//orig get_pmctr_ctl r14, r12 // read shadow pmctr ctl; r12=adjusted impure pointer
+ mfpr r12, pt_impure
+ lda r12, CNS_Q_IPR(r12)
+ RESTORE_SHADOW(r14,CNS_Q_PM_CTL,r12);
+
+ lda r8, 0x3F(r31)
+//orig sll r8, pmctr_ctl_v_frq2, r8 // build mask for frequency select field
+// I guess this should be a shift of 4 bits from the above control register structure
+#define pmctr_ctl_v_frq2_SHIFT 4
+ sll r8, pmctr_ctl_v_frq2_SHIFT, r8 // build mask for frequency select field
+
+ and r8, r17, r17
+ bic r14, r8, r14 // clear out old frequency select bits
+
+ or r17, r14, r14 // or in new frequency select info
+//orig store_reg1 pmctr_ctl, r14, r12, ipr=1 // update pmctr_ctl register
+ SAVE_SHADOW(r14,CNS_Q_PM_CTL,r12); // r12 still has the adjusted impure ptr
+
+ br r31, perfmon_success
+
+// read counters
+perfmon_rd:
+ mfpr r0, ev5__pmctr
+ or r0, 1, r0 // or in return status
+ hw_rei // back to user
+
+// write counters
+perfmon_wr:
+ mfpr r14, ev5__pmctr
+ lda r8, 0x3FFF(r31) // ctr2<13:0> mask
+ sll r8, pmctr_v_ctr2, r8
+
+ LDLI(r9, (0xFFFFFFFF)) // ctr2<15:0>,ctr1<15:0> mask
+ sll r9, pmctr_v_ctr1, r9
+ or r8, r9, r8 // or ctr2, ctr1, ctr0 mask
+ bic r14, r8, r14 // clear ctr fields
+ and r17, r8, r25 // clear all but ctr fields
+ or r25, r14, r14 // write ctr fields
+ mtpr r14, ev5__pmctr // update pmctr ipr
+
+ mfpr r31, pt0 // pad pmctr write (needed only to keep PVC happy)
+
+perfmon_success:
+ or r31, 1, r0 // set success
+ hw_rei // back to user
+
+perfmon_unknown:
+ or r31, r31, r0 // set fail
+ hw_rei // back to user
+
+
+//////////////////////////////////////////////////////////
+// Copy code
+//////////////////////////////////////////////////////////
+
+copypal_impl:
+ mov r16, r0
+#ifdef CACHE_COPY
+#ifndef CACHE_COPY_UNALIGNED
+ and r16, 63, r8
+ and r17, 63, r9
+ bis r8, r9, r8
+ bne r8, cache_copy_done
+#endif
+ bic r18, 63, r8
+ and r18, 63, r18
+ beq r8, cache_copy_done
+cache_loop:
+ ldf f17, 0(r16)
+ stf f17, 0(r16)
+ addq r17, 64, r17
+ addq r16, 64, r16
+ subq r8, 64, r8
+ bne r8, cache_loop
+cache_copy_done:
+#endif
+ ble r18, finished // if len <=0 we are finished
+ ldq_u r8, 0(r17)
+ xor r17, r16, r9
+ and r9, 7, r9
+ and r16, 7, r10
+ bne r9, unaligned
+ beq r10, aligned
+ ldq_u r9, 0(r16)
+ addq r18, r10, r18
+ mskqh r8, r17, r8
+ mskql r9, r17, r9
+ bis r8, r9, r8
+aligned:
+ subq r18, 1, r10
+ bic r10, 7, r10
+ and r18, 7, r18
+ beq r10, aligned_done
+loop:
+ stq_u r8, 0(r16)
+ ldq_u r8, 8(r17)
+ subq r10, 8, r10
+ lda r16,8(r16)
+ lda r17,8(r17)
+ bne r10, loop
+aligned_done:
+ bne r18, few_left
+ stq_u r8, 0(r16)
+ br r31, finished
+ few_left:
+ mskql r8, r18, r10
+ ldq_u r9, 0(r16)
+ mskqh r9, r18, r9
+ bis r10, r9, r10
+ stq_u r10, 0(r16)
+ br r31, finished
+unaligned:
+ addq r17, r18, r25
+ cmpule r18, 8, r9
+ bne r9, unaligned_few_left
+ beq r10, unaligned_dest_aligned
+ and r16, 7, r10
+ subq r31, r10, r10
+ addq r10, 8, r10
+ ldq_u r9, 7(r17)
+ extql r8, r17, r8
+ extqh r9, r17, r9
+ bis r8, r9, r12
+ insql r12, r16, r12
+ ldq_u r13, 0(r16)
+ mskql r13, r16, r13
+ bis r12, r13, r12
+ stq_u r12, 0(r16)
+ addq r16, r10, r16
+ addq r17, r10, r17
+ subq r18, r10, r18
+ ldq_u r8, 0(r17)
+unaligned_dest_aligned:
+ subq r18, 1, r10
+ bic r10, 7, r10
+ and r18, 7, r18
+ beq r10, unaligned_partial_left
+unaligned_loop:
+ ldq_u r9, 7(r17)
+ lda r17, 8(r17)
+ extql r8, r17, r12
+ extqh r9, r17, r13
+ subq r10, 8, r10
+ bis r12, r13, r13
+ stq r13, 0(r16)
+ lda r16, 8(r16)
+ beq r10, unaligned_second_partial_left
+ ldq_u r8, 7(r17)
+ lda r17, 8(r17)
+ extql r9, r17, r12
+ extqh r8, r17, r13
+ bis r12, r13, r13
+ subq r10, 8, r10
+ stq r13, 0(r16)
+ lda r16, 8(r16)
+ bne r10, unaligned_loop
+unaligned_partial_left:
+ mov r8, r9
+unaligned_second_partial_left:
+ ldq_u r8, -1(r25)
+ extql r9, r17, r9
+ extqh r8, r17, r8
+ bis r8, r9, r8
+ bne r18, few_left
+ stq_u r8, 0(r16)
+ br r31, finished
+unaligned_few_left:
+ ldq_u r9, -1(r25)
+ extql r8, r17, r8
+ extqh r9, r17, r9
+ bis r8, r9, r8
+ insqh r8, r16, r9
+ insql r8, r16, r8
+ lda r12, -1(r31)
+ mskql r12, r18, r13
+ cmovne r13, r13, r12
+ insqh r12, r16, r13
+ insql r12, r16, r12
+ addq r16, r18, r10
+ ldq_u r14, 0(r16)
+ ldq_u r25, -1(r10)
+ bic r14, r12, r14
+ bic r25, r13, r25
+ and r8, r12, r8
+ and r9, r13, r9
+ bis r8, r14, r8
+ bis r9, r25, r9
+ stq_u r9, -1(r10)
+ stq_u r8, 0(r16)
+finished:
+ hw_rei
diff --git a/system/alpha/palcode/platform.S b/system/alpha/palcode/platform.S
new file mode 100644
index 000000000..da3f466c1
--- /dev/null
+++ b/system/alpha/palcode/platform.S
@@ -0,0 +1,2337 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 1993 Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali G. Saidi
+ * Nathan L. Binkert
+ */
+
+#define max_cpuid 1
+#define hw_rei_spe hw_rei
+
+#include "ev5_defs.h"
+#include "ev5_impure.h"
+#include "ev5_alpha_defs.h"
+#include "ev5_paldef.h"
+#include "ev5_osfalpha_defs.h"
+#include "fromHudsonMacros.h"
+#include "fromHudsonOsf.h"
+#include "dc21164FromGasSources.h"
+#include "cserve.h"
+#include "tlaser.h"
+
+#define pt_entInt pt_entint
+#define pt_entArith pt_entarith
+#define mchk_size ((mchk_cpu_base + 7 + 8) &0xfff8)
+#define mchk_flag CNS_Q_FLAG
+#define mchk_sys_base 56
+#define mchk_cpu_base (CNS_Q_LD_LOCK + 8)
+#define mchk_offsets CNS_Q_EXC_ADDR
+#define mchk_mchk_code 8
+#define mchk_ic_perr_stat CNS_Q_ICPERR_STAT
+#define mchk_dc_perr_stat CNS_Q_DCPERR_STAT
+#define mchk_sc_addr CNS_Q_SC_ADDR
+#define mchk_sc_stat CNS_Q_SC_STAT
+#define mchk_ei_addr CNS_Q_EI_ADDR
+#define mchk_bc_tag_addr CNS_Q_BC_TAG_ADDR
+#define mchk_fill_syn CNS_Q_FILL_SYN
+#define mchk_ei_stat CNS_Q_EI_STAT
+#define mchk_exc_addr CNS_Q_EXC_ADDR
+#define mchk_ld_lock CNS_Q_LD_LOCK
+#define osfpcb_q_Ksp pcb_q_ksp
+#define pal_impure_common_size ((0x200 + 7) & 0xfff8)
+
+#if defined(BIG_TSUNAMI)
+#define MAXPROC 0x3f
+#define IPIQ_addr 0x800
+#define IPIQ_shift 0
+#define IPIR_addr 0x840
+#define IPIR_shift 0
+#define RTC_addr 0x880
+#define RTC_shift 0
+#define DIR_addr 0xa2
+#elif defined(TSUNAMI)
+#define MAXPROC 0x3
+#define IPIQ_addr 0x080
+#define IPIQ_shift 12
+#define IPIR_addr 0x080
+#define IPIR_shift 8
+#define RTC_addr 0x080
+#define RTC_shift 4
+#define DIR_addr 0xa0
+#elif defined(TLASER)
+#define MAXPROC 0xf
+#else
+#error Must define BIG_TSUNAMI, TSUNAMI, or TLASER
+#endif
+
+#define ALIGN_BLOCK \
+ .align 5
+
+#define ALIGN_BRANCH \
+ .align 3
+
+#define EXPORT(_x) \
+ .align 5; \
+ .globl _x; \
+_x:
+
+// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
+// XXX the following is 'made up'
+// XXX bugnion
+
+// XXX bugnion not sure how to align 'quad'
+#define ALIGN_QUAD \
+ .align 3
+
+#define ALIGN_128 \
+ .align 7
+
+
+#define GET_IMPURE(_r) mfpr _r,pt_impure
+#define GET_ADDR(_r1,_off,_r2) lda _r1,_off(_r2)
+
+
+#define BIT(_x) (1<<(_x))
+
+
+// System specific code - beh model version
+//
+//
+// Entry points
+// SYS_CFLUSH - Cache flush
+// SYS_CSERVE - Console service
+// SYS_WRIPIR - interprocessor interrupts
+// SYS_HALT_INTERRUPT - Halt interrupt
+// SYS_PASSIVE_RELEASE - Interrupt, passive release
+// SYS_INTERRUPT - Interrupt
+// SYS_RESET - Reset
+// SYS_ENTER_CONSOLE
+//
+//
+// Macro to read TLINTRSUMx
+//
+// Based on the CPU_NUMBER, read either the TLINTRSUM0 or TLINTRSUM1 register
+//
+// Assumed register usage:
+// rsum TLINTRSUMx contents
+// raddr node space address
+// scratch scratch register
+//
+#define Read_TLINTRSUMx(_rsum, _raddr, _scratch) \
+ nop; \
+ mfpr _scratch, pt_whami; /* Get our whami (VID) */ \
+ extbl _scratch, 1, _scratch; /* shift down to bit 0 */ \
+ lda _raddr, 0xff88(zero); /* Get base node space address bits */ \
+ sll _raddr, 24, _raddr; /* Shift up to proper position */ \
+ srl _scratch, 1, _rsum; /* Shift off the cpu number */ \
+ sll _rsum, 22, _rsum; /* Get our node offset */ \
+ addq _raddr, _rsum, _raddr; /* Get our base node space address */ \
+ blbs _scratch, 1f; \
+ lda _raddr, 0x1180(_raddr); \
+ br r31, 2f; \
+1: lda _raddr, 0x11c0(_raddr); \
+2: ldl_p _rsum, 0(_raddr) /* read the right tlintrsum reg */
+
+//
+// Macro to write TLINTRSUMx
+//
+// Based on the CPU_NUMBER, write either the TLINTRSUM0 or TLINTRSUM1 register
+//
+// Assumed register usage:
+// rsum TLINTRSUMx write data
+// raddr node space address
+// scratch scratch register
+//
+#define Write_TLINTRSUMx(_rsum,_raddr,_whami) \
+ nop; \
+ mfpr _whami, pt_whami; /* Get our whami (VID) */ \
+ extbl _whami, 1, _whami; /* shift down to bit 0 */ \
+ lda _raddr, 0xff88(zero); /* Get base node space address bits */ \
+ sll _raddr, 24, _raddr; /* Shift up to proper position */ \
+ blbs _whami, 1f; \
+ lda _raddr, 0x1180(_raddr); \
+ br zero, 2f; \
+1: lda _raddr, 0x11c0(_raddr); \
+2: srl _whami, 1, _whami; /* Get our node offset */ \
+ addq _raddr, _whami, _raddr; /* Get our base node space address */ \
+ mb; \
+ stq_p _rsum, 0(_raddr); /* write the right tlintrsum reg */ \
+ ldq_p _rsum, 0(_raddr); /* dummy read to tlintrsum */ \
+ bis _rsum, _rsum, _rsum /* needed to complete the ldqp above */
+
+
+//
+// Macro to determine highest priority TIOP Node ID from interrupt pending mask
+//
+// Assumed register usage:
+// rmask - TLINTRSUMx contents, shifted to isolate IOx bits
+// rid - TLSB Node ID of highest TIOP
+//
+#define Intr_Find_TIOP(_rmask,_rid) \
+ srl _rmask,3,_rid; /* check IOP8 */ \
+ blbc _rid,1f; /* not IOP8 */ \
+ lda _rid,8(zero); /* IOP8 */ \
+ br zero,6f; \
+1: srl _rmask,3,_rid; /* check IOP7 */ \
+ blbc _rid, 2f; /* not IOP7 */ \
+ lda _rid, 7(r31); /* IOP7 */ \
+ br r31, 6f; \
+2: srl _rmask, 2, _rid; /* check IOP6 */ \
+ blbc _rid, 3f; /* not IOP6 */ \
+ lda _rid, 6(r31); /* IOP6 */ \
+ br r31, 6f; \
+3: srl _rmask, 1, _rid; /* check IOP5 */ \
+ blbc _rid, 4f; /* not IOP5 */ \
+ lda _rid, 5(r31); /* IOP5 */ \
+ br r31, 6f; \
+4: srl _rmask, 0, _rid; /* check IOP4 */ \
+ blbc _rid, 5f; /* not IOP4 */ \
+ lda r14, 4(r31); /* IOP4 */ \
+ br r31, 6f; \
+5: lda r14, 0(r31); /* passive release */ \
+6:
+
+//
+// Macro to calculate base node space address for given node id
+//
+// Assumed register usage:
+// rid - TLSB node id
+// raddr - base node space address
+#define Get_TLSB_Node_Address(_rid,_raddr) \
+ sll _rid, 22, _rid; \
+ lda _raddr, 0xff88(zero); \
+ sll _raddr, 24, _raddr; \
+ addq _raddr, _rid, _raddr
+
+
+#define OSFmchk_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
+ lda _rs1, tlep_##_tlepreg(zero); \
+ or _rs1, _nodebase, _rs1; \
+ ldl_p _rs1, 0(_rs1); \
+ stl_p _rs, mchk_##_tlepreg(_rlog) /* store in frame */
+
+#define OSFmchk_TLEPstore(_tlepreg) \
+ OSFmchk_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
+
+#define OSFcrd_TLEPstore_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
+ lda _rs1, tlep_##_tlepreg(zero); \
+ or _rs1, _nodebase, _rs1; \
+ ldl_p _rs1, 0(_rs1); \
+ stl_p _rs, mchk_crd_##_tlepreg(_rlog)
+
+#define OSFcrd_TLEPstore_tlsb_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
+ lda _rs1, tlsb_##_tlepreg(zero); \
+ or _rs1, _nodebase, _rs1; \
+ ldl_p _rs1, 0(_rs1); \
+ stl_p _rs,mchk_crd_##_tlepreg(_rlog)
+
+#define OSFcrd_TLEPstore_tlsb_clr_1(_rlog,_rs,_rs1,_nodebase,_tlepreg) \
+ lda _rs1,tlsb_##_tlepreg(zero); \
+ or _rs1, _nodebase,_rs1; \
+ ldl_p _rs1, 0(_rs1); \
+ stl_p _rs, mchk_crd_##_tlepreg(_rlog); \
+ stl_p _rs, 0(_rs1)
+
+#define OSFcrd_TLEPstore(_tlepreg) \
+ OSFcrd_TLEPstore_1(r14,r8,r4,r13,_tlepreg)
+#define OSFcrd_TLEPstore_tlsb(_tlepreg) \
+ OSFcrd_TLEPstore_tlsb_1(r14,r8,r4,r13,_tlepreg)
+#define OSFcrd_TLEPstore_tlsb_clr(_tlepreg) \
+ OSFcrd_TLEPstore_tlsb_clr_1(r14,r8,r4,r13,_tlepreg)
+
+
+#define save_pcia_intr(_irq) \
+ and r13, 0xf, r25; /* isolate low 4 bits */ \
+ addq r14, 4, r14; /* format the TIOP Node id field */ \
+ sll r14, 4, r14; /* shift the TIOP Node id */ \
+ or r14, r25, r10; /* merge Node id/hose/HPC */ \
+ mfpr r14, pt14; /* get saved value */ \
+ extbl r14, _irq, r25; /* confirm none outstanding */ \
+ bne r25, sys_machine_check_while_in_pal; \
+ insbl r10, _irq, r10; /* align new info */ \
+ or r14, r10, r14; /* merge info */ \
+ mtpr r14, pt14; /* save it */ \
+ bic r13, 0xf, r13 /* clear low 4 bits of vector */
+
+
+// wripir - PALcode for wripir instruction
+// R16 has the processor number.
+//
+ ALIGN_BLOCK
+EXPORT(sys_wripir)
+ //
+ // Convert the processor number to a CPU mask
+ //
+ and r16, MAXPROC, r14 // mask the top stuff: MAXPROC+1 CPUs supported
+ bis r31, 0x1, r16 // get a one
+ sll r16, r14, r14 // shift the bit to the right place
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ sll r14,IPIQ_shift,r14
+#endif
+
+
+ //
+ // Build the Broadcast Space base address
+ //
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ lda r16,0xf01(r31)
+ sll r16,32,r16
+ ldah r13,0xa0(r31)
+ sll r13,8,r13
+ bis r16,r13,r16
+ lda r16,IPIQ_addr(r16)
+#elif defined(TLASER)
+ lda r13, 0xff8e(r31) // Load the upper address bits
+ sll r13, 24, r13 // shift them to the top
+#endif
+
+ //
+ // Send out the IP Intr
+ //
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ stq_p r14, 0(r16) // Tsunami MISC Register
+#elif defined(TLASER)
+ stq_p r14, 0x40(r13) // Write to TLIPINTR reg
+#endif
+ wmb // Push out the store
+ hw_rei
+
+
+// cflush - PALcode for CFLUSH instruction
+//
+// SYS_CFLUSH
+// Entry:
+// R16 - contains the PFN of the page to be flushed
+//
+// Function:
+// Flush all Dstream caches of 1 entire page
+//
+//
+ ALIGN_BLOCK
+EXPORT(sys_cflush)
+
+// #convert pfn to addr, and clean off <63:20>
+// #sll r16, <page_offset_size_bits>+<63-20>>, r12
+ sll r16, page_offset_size_bits+(63-20),r12
+
+// #ldah r13,<<1@22>+32768>@-16(r31)// + xxx<31:16>
+// # stolen from srcmax code. XXX bugnion
+ lda r13, 0x10(r31) // assume 16Mbytes of cache
+ sll r13, 20, r13 // convert to bytes
+
+
+ srl r12, 63-20, r12 // shift back to normal position
+ xor r12, r13, r12 // xor addr<18>
+
+ or r31, 8192/(32*8), r13 // get count of loads
+ nop
+
+cflush_loop:
+ subq r13, 1, r13 // decr counter
+ mfpr r25, ev5__intid // Fetch level of interruptor
+
+ ldq_p r31, 32*0(r12) // do a load
+ ldq_p r31, 32*1(r12) // do next load
+
+ ldq_p r31, 32*2(r12) // do next load
+ ldq_p r31, 32*3(r12) // do next load
+
+ ldq_p r31, 32*4(r12) // do next load
+ ldq_p r31, 32*5(r12) // do next load
+
+ ldq_p r31, 32*6(r12) // do next load
+ ldq_p r31, 32*7(r12) // do next load
+
+ mfpr r14, ev5__ipl // Fetch current level
+ lda r12, (32*8)(r12) // skip to next cache block addr
+
+ cmple r25, r14, r25 // R25 = 1 if intid .less than or eql ipl
+ beq r25, 1f // if any int's pending, re-queue CFLUSH -- need to check for hlt interrupt???
+
+ bne r13, cflush_loop // loop till done
+ hw_rei // back to user
+
+ ALIGN_BRANCH
+1: // Here if interrupted
+ mfpr r12, exc_addr
+ subq r12, 4, r12 // Backup PC to point to CFLUSH
+
+ mtpr r12, exc_addr
+ nop
+
+ mfpr r31, pt0 // Pad exc_addr write
+ hw_rei
+
+
+ ALIGN_BLOCK
+//
+// sys_cserve - PALcode for CSERVE instruction
+//
+// Function:
+// Various functions for private use of console software
+//
+// option selector in r0
+// arguments in r16....
+//
+//
+// r0 = 0 unknown
+//
+// r0 = 1 ldq_p
+// r0 = 2 stq_p
+// args, are as for normal STQ_P/LDQ_P in VMS PAL
+//
+// r0 = 3 dump_tb's
+// r16 = detination PA to dump tb's to.
+//
+// r0<0> = 1, success
+// r0<0> = 0, failure, or option not supported
+// r0<63:1> = (generally 0, but may be function dependent)
+// r0 - load data on ldq_p
+//
+//
+EXPORT(sys_cserve)
+
+ /* taken from scrmax */
+ cmpeq r18, CSERVE_K_RD_IMPURE, r0
+ bne r0, Sys_Cserve_Rd_Impure
+
+ cmpeq r18, CSERVE_K_JTOPAL, r0
+ bne r0, Sys_Cserve_Jtopal
+ call_pal 0
+
+ or r31, r31, r0
+ hw_rei // and back we go
+
+Sys_Cserve_Rd_Impure:
+ mfpr r0, pt_impure // Get base of impure scratch area.
+ hw_rei
+
+ ALIGN_BRANCH
+
+Sys_Cserve_Jtopal:
+ bic a0, 3, t8 // Clear out low 2 bits of address
+ bis t8, 1, t8 // Or in PAL mode bit
+ mtpr t8,exc_addr
+ hw_rei
+
+ // ldq_p
+ ALIGN_QUAD
+1:
+ ldq_p r0,0(r17) // get the data
+ nop // pad palshadow write
+
+ hw_rei // and back we go
+
+
+ // stq_p
+ ALIGN_QUAD
+2:
+ stq_p r18, 0(r17) // store the data
+ lda r0,17(r31) // bogus
+ hw_rei // and back we go
+
+
+ ALIGN_QUAD
+csrv_callback:
+ ldq r16, 0(r17) // restore r16
+ ldq r17, 8(r17) // restore r17
+ lda r0, hlt_c_callback(r31)
+ br r31, sys_enter_console
+
+
+csrv_identify:
+ mfpr r0, pal_base
+ ldq_p r0, 8(r0)
+ hw_rei
+
+
+// dump tb's
+ ALIGN_QUAD
+0:
+ // DTB PTEs - 64 entries
+ addq r31, 64, r0 // initialize loop counter
+ nop
+
+1: mfpr r12, ev5__dtb_pte_temp // read out next pte to temp
+ mfpr r12, ev5__dtb_pte // read out next pte to reg file
+
+ subq r0, 1, r0 // decrement loop counter
+ nop // Pad - no Mbox instr in cycle after mfpr
+
+ stq_p r12, 0(r16) // store out PTE
+ addq r16, 8 ,r16 // increment pointer
+
+ bne r0, 1b
+
+ ALIGN_BRANCH
+ // ITB PTEs - 48 entries
+ addq r31, 48, r0 // initialize loop counter
+ nop
+
+2: mfpr r12, ev5__itb_pte_temp // read out next pte to temp
+ mfpr r12, ev5__itb_pte // read out next pte to reg file
+
+ subq r0, 1, r0 // decrement loop counter
+ nop //
+
+ stq_p r12, 0(r16) // store out PTE
+ addq r16, 8 ,r16 // increment pointer
+
+ bne r0, 2b
+ or r31, 1, r0 // set success
+
+ hw_rei // and back we go
+
+
+//
+// SYS_INTERRUPT - Interrupt processing code
+//
+// Current state:
+// Stack is pushed
+// ps, sp and gp are updated
+// r12, r14 - available
+// r13 - INTID (new EV5 IPL)
+// r25 - ISR
+// r16, r17, r18 - available
+//
+//
+EXPORT(sys_interrupt)
+ cmpeq r13, 31, r12 // Check for level 31 interrupt
+ bne r12, sys_int_mchk_or_crd // machine check or crd
+
+ cmpeq r13, 30, r12 // Check for level 30 interrupt
+ bne r12, sys_int_powerfail // powerfail
+
+ cmpeq r13, 29, r12 // Check for level 29 interrupt
+ bne r12, sys_int_perf_cnt // performance counters
+
+ cmpeq r13, 23, r12 // Check for level 23 interrupt
+ bne r12, sys_int_23 // IPI in Tsunami
+
+ cmpeq r13, 22, r12 // Check for level 22 interrupt
+ bne r12, sys_int_22 // timer interrupt
+
+ cmpeq r13, 21, r12 // Check for level 21 interrupt
+ bne r12, sys_int_21 // I/O
+
+ cmpeq r13, 20, r12 // Check for level 20 interrupt
+ bne r12, sys_int_20 // system error interrupt
+ // (might be corrected)
+
+ mfpr r14, exc_addr // ooops, something is wrong
+ br r31, pal_pal_bug_check_from_int
+
+
+//
+//sys_int_2*
+// Routines to handle device interrupts at IPL 23-20.
+// System specific method to ack/clear the interrupt, detect passive
+// release, detect interprocessor (22), interval clock (22), corrected
+// system error (20)
+//
+// Current state:
+// Stack is pushed
+// ps, sp and gp are updated
+// r12, r14 - available
+// r13 - INTID (new EV5 IPL)
+// r25 - ISR
+//
+// On exit:
+// Interrupt has been ack'd/cleared
+// a0/r16 - signals IO device interrupt
+// a1/r17 - contains interrupt vector
+// exit to ent_int address
+//
+//
+
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ ALIGN_BRANCH
+sys_int_23:
+ or r31,0,r16 // IPI interrupt A0 = 0
+ lda r12,0xf01(r31) // build up an address for the MISC register
+ sll r12,16,r12
+ lda r12,0xa000(r12)
+ sll r12,16,r12
+ lda r12,IPIR_addr(r12)
+
+ mfpr r10, pt_whami // get CPU ID
+ extbl r10, 1, r10 // Isolate just whami bits
+ or r31,0x1,r14 // load r14 with bit to clear
+ sll r14,r10,r14 // left shift by CPU ID
+ sll r14,IPIR_shift,r14
+ stq_p r14, 0(r12) // clear the ipi interrupt
+
+ br r31, pal_post_interrupt // Notify the OS
+
+
+ ALIGN_BRANCH
+sys_int_22:
+ or r31,1,r16 // a0 means it is a clock interrupt
+ lda r12,0xf01(r31) // build up an address for the MISC register
+ sll r12,16,r12
+ lda r12,0xa000(r12)
+ sll r12,16,r12
+ lda r12,RTC_addr(r12)
+
+ mfpr r10, pt_whami // get CPU ID
+ extbl r10, 1, r10 // Isolate just whami bits
+ or r31,0x1,r14 // load r14 with bit to clear
+ sll r14,r10,r14 // left shift by CPU ID
+ sll r14,RTC_shift,r14 // put the bits in the right position
+ stq_p r14, 0(r12) // clear the rtc interrupt
+
+ br r31, pal_post_interrupt // Tell the OS
+
+
+ ALIGN_BRANCH
+sys_int_20:
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ srl r13, 12, r13 // shift down to examine IPL15
+
+ Intr_Find_TIOP(r13,r14)
+ beq r14, 1f
+
+ Get_TLSB_Node_Address(r14,r10)
+ lda r10, 0xa40(r10) // Get base TLILID address
+
+ ldl_p r13, 0(r10) // Read the TLILID register
+ bne r13, pal_post_dev_interrupt
+ beq r13, 1f
+
+ and r13, 0x3, r10 // check for PCIA bits
+ beq r10, pal_post_dev_interrupt // done if nothing set
+ save_pcia_intr(1)
+ br r31, pal_post_dev_interrupt //
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+sys_int_21:
+
+ lda r12,0xf01(r31) // calculate DIRn address
+ sll r12,32,r12
+ ldah r13,DIR_addr(r31)
+ sll r13,8,r13
+ bis r12,r13,r12
+
+ mfpr r13, pt_whami // get CPU ID
+ extbl r13, 1, r13 // Isolate just whami bits
+
+#ifdef BIG_TSUNAMI
+ sll r13,4,r13
+ or r12,r13,r12
+#else
+ lda r12,0x0080(r12)
+ and r13,0x1,r14 // grab LSB and shift left 6
+ sll r14,6,r14
+ and r13,0x2,r10 // grabl LSB+1 and shift left 9
+ sll r10,9,r10
+
+ mskbl r12,0,r12 // calculate DIRn address
+ lda r13,0x280(r31)
+ bis r12,r13,r12
+ or r12,r14,r12
+ or r12,r10,r12
+#endif
+
+ ldq_p r13, 0(r12) // read DIRn
+
+ or r31,1,r14 // set bit 55 (ISA Interrupt)
+ sll r14,55,r14
+
+ and r13, r14, r14 // check if bit 55 is set
+ lda r16,0x900(r31) // load offset for normal into r13
+ beq r14, normal_int // if not compute the vector normally
+
+ lda r16,0x800(r31) // replace with offset for pic
+ lda r12,0xf01(r31) // build an addr to access PIC
+ sll r12,32,r12 // at f01fc000000
+ ldah r13,0xfc(r31)
+ sll r13,8,r13
+ bis r12,r13,r12
+ ldq_p r13,0x0020(r12) // read PIC1 ISR for interrupting dev
+
+normal_int:
+ //ctlz r13,r14 // count the number of leading zeros
+ // EV5 doesn't have ctlz, but we do, so lets use it
+ .byte 0x4e
+ .byte 0x06
+ .byte 0xed
+ .byte 0x73
+ lda r10,63(r31)
+ subq r10,r14,r17 // subtract from
+
+ lda r13,0x10(r31)
+ mulq r17,r13,r17 // compute 0x900 + (0x10 * Highest DIRn-bit)
+ addq r17,r16,r17
+
+ or r31,3,r16 // a0 means it is a I/O interrupt
+
+ br r31, pal_post_interrupt
+
+#elif defined(TLASER)
+ ALIGN_BRANCH
+sys_int_23:
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ srl r13, 22, r13 // shift down to examine IPL17
+
+ Intr_Find_TIOP(r13,r14)
+ beq r14, 1f
+
+ Get_TLSB_Node_Address(r14,r10)
+ lda r10, 0xac0(r10) // Get base TLILID address
+
+ ldl_p r13, 0(r10) // Read the TLILID register
+ bne r13, pal_post_dev_interrupt
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+sys_int_22:
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ srl r13, 6, r14 // check the Intim bit
+
+ blbs r14, tlep_intim // go service Intim
+ srl r13, 5, r14 // check the IP Int bit
+
+ blbs r14, tlep_ipint // go service IP Int
+ srl r13, 17, r13 // shift down to examine IPL16
+
+ Intr_Find_TIOP(r13,r14)
+ beq r14, 1f
+
+ Get_TLSB_Node_Address(r14,r10)
+ lda r10, 0xa80(r10) // Get base TLILID address
+
+ ldl_p r13, 0(r10) // Read the TLILID register
+ bne r13, pal_post_dev_interrupt
+ beq r13, 1f
+
+ and r13, 0x3, r10 // check for PCIA bits
+ beq r10, pal_post_dev_interrupt // done if nothing set
+ save_pcia_intr(2)
+ br r31, pal_post_dev_interrupt //
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+sys_int_21:
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ srl r13, 12, r13 // shift down to examine IPL15
+
+ Intr_Find_TIOP(r13,r14)
+ beq r14, 1f
+
+ Get_TLSB_Node_Address(r14,r10)
+ lda r10, 0xa40(r10) // Get base TLILID address
+
+ ldl_p r13, 0(r10) // Read the TLILID register
+ bne r13, pal_post_dev_interrupt
+ beq r13, 1f
+
+ and r13, 0x3, r10 // check for PCIA bits
+ beq r10, pal_post_dev_interrupt // done if nothing set
+ save_pcia_intr(1)
+ br r31, pal_post_dev_interrupt //
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+sys_int_20:
+ lda r13, 1(r31) // Duart0 bit
+ Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
+
+ Read_TLINTRSUMx(r13,r10,r14) // read the right TLINTRSUMx
+ blbs r13, tlep_uart0 // go service UART int
+
+ srl r13, 7, r13 // shift down to examine IPL14
+ Intr_Find_TIOP(r13,r14)
+
+ beq r14, tlep_ecc // Branch if not IPL14
+ Get_TLSB_Node_Address(r14,r10)
+
+ lda r10, 0xa00(r10) // Get base TLILID0 address
+ ldl_p r13, 0(r10) // Read the TLILID register
+
+ bne r13, pal_post_dev_interrupt
+ beq r13, 1f
+
+ and r13, 0x3, r10 // check for PCIA bits
+ beq r10, pal_post_dev_interrupt // done if nothing set
+ save_pcia_intr(0)
+ br r31, pal_post_dev_interrupt //
+1: lda r16, osfint_c_passrel(r31) // passive release
+ br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+tlep_intim:
+ lda r13, 0xffb(r31) // get upper GBUS address bits
+ sll r13, 28, r13 // shift up to top
+
+ lda r13, (0x300)(r13) // full CSRC address (tlep watch csrc offset)
+ ldq_p r13, 0(r13) // read CSRC
+
+ lda r13, 0x40(r31) // load Intim bit
+ Write_TLINTRSUMx(r13,r10,r14) // clear the Intim bit
+
+ lda r16, osfint_c_clk(r31) // passive release
+ br r31, pal_post_interrupt // Build the stack frame
+
+
+ ALIGN_BRANCH
+tlep_ipint:
+ lda r13, 0x20(r31) // load IP Int bit
+ Write_TLINTRSUMx(r13,r10,r14) // clear the IP Int bit
+
+ lda r16, osfint_c_ip(r31) // passive release
+ br r31, pal_post_interrupt // Build the stack frame
+
+
+ ALIGN_BRANCH
+tlep_uart0:
+ lda r13, 0xffa(r31) // get upper GBUS address bits
+ sll r13, 28, r13 // shift up to top
+
+ ldl_p r14, 0x80(r13) // zero pointer register
+ lda r14, 3(r31) // index to RR3
+
+ stl_p r14, 0x80(r13) // write pointer register
+ mb
+
+ mb
+ ldl_p r14, 0x80(r13) // read RR3
+
+ srl r14, 5, r10 // is it Channel A RX?
+ blbs r10, uart0_rx
+
+ srl r14, 4, r10 // is it Channel A TX?
+ blbs r10, uart0_tx
+
+ srl r14, 2, r10 // is it Channel B RX?
+ blbs r10, uart1_rx
+
+ srl r14, 1, r10 // is it Channel B TX?
+ blbs r10, uart1_tx
+
+ lda r8, 0(r31) // passive release
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+uart0_rx:
+ lda r8, 0x680(r31) // UART0 RX vector
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+uart0_tx:
+ lda r14, 0x28(r31) // Reset TX Int Pending code
+ mb
+ stl_p r14, 0x80(r13) // write Channel A WR0
+ mb
+
+ lda r8, 0x6c0(r31) // UART0 TX vector
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+uart1_rx:
+ lda r8, 0x690(r31) // UART1 RX vector
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+uart1_tx:
+ lda r14, 0x28(r31) // Reset TX Int Pending code
+ stl_p r14, 0(r13) // write Channel B WR0
+
+ lda r8, 0x6d0(r31) // UART1 TX vector
+ br r31, clear_duart0_int // clear tlintrsum and post
+
+
+ ALIGN_BRANCH
+clear_duart0_int:
+ lda r13, 1(r31) // load duart0 bit
+ Write_TLINTRSUMx(r13,r10,r14) // clear the duart0 bit
+
+ beq r8, 1f
+ or r8, r31, r13 // move vector to r13
+ br r31, pal_post_dev_interrupt // Build the stack frame
+1: nop
+ nop
+ hw_rei
+// lda r16, osfint_c_passrel(r31) // passive release
+// br r31, pal_post_interrupt //
+
+
+ ALIGN_BRANCH
+tlep_ecc:
+ mfpr r14, pt_whami // get our node id
+ extbl r14, 1, r14 // shift to bit 0
+
+ srl r14, 1, r14 // shift off cpu number
+ Get_TLSB_Node_Address(r14,r10) // compute our nodespace address
+
+ ldl_p r13, 0x40(r10) // read our TLBER WAS tlsb_tlber_offset
+ srl r13, 17, r13 // shift down the CWDE/CRDE bits
+
+ and r13, 3, r13 // mask the CWDE/CRDE bits
+ beq r13, 1f
+
+ ornot r31, r31, r12 // set flag
+ lda r9, mchk_c_sys_ecc(r31) // System Correctable error MCHK code
+ br r31, sys_merge_sys_corr // jump to CRD logout frame code
+
+1: lda r16, osfint_c_passrel(r31) // passive release
+
+#endif // if TSUNAMI || BIG_TSUNAMI elif TLASER
+
+ ALIGN_BRANCH
+pal_post_dev_interrupt:
+ or r13, r31, r17 // move vector to a1
+ or r31, osfint_c_dev, r16 // a0 signals IO device interrupt
+
+pal_post_interrupt:
+ mfpr r12, pt_entint
+
+ mtpr r12, exc_addr
+
+ nop
+ nop
+
+ hw_rei_spe
+
+
+//
+// sys_passive_release
+// Just pretend the interrupt never occurred.
+//
+
+EXPORT(sys_passive_release)
+ mtpr r11, ev5__dtb_cm // Restore Mbox current mode for ps
+ nop
+
+ mfpr r31, pt0 // Pad write to dtb_cm
+ hw_rei
+
+//
+// sys_int_powerfail
+// A powerfail interrupt has been detected. The stack has been pushed.
+// IPL and PS are updated as well.
+//
+// I'm not sure what to do here, I'm treating it as an IO device interrupt
+//
+//
+
+ ALIGN_BLOCK
+sys_int_powerfail:
+ lda r12, 0xffc4(r31) // get GBUS_MISCR address bits
+ sll r12, 24, r12 // shift to proper position
+ ldq_p r12, 0(r12) // read GBUS_MISCR
+ srl r12, 5, r12 // isolate bit <5>
+ blbc r12, 1f // if clear, no missed mchk
+
+ // Missed a CFAIL mchk
+ lda r13, 0xffc7(r31) // get GBUS$SERNUM address bits
+ sll r13, 24, r13 // shift to proper position
+ lda r14, 0x40(r31) // get bit <6> mask
+ ldq_p r12, 0(r13) // read GBUS$SERNUM
+ or r12, r14, r14 // set bit <6>
+ stq_p r14, 0(r13) // clear GBUS$SERNUM<6>
+ mb
+ mb
+
+1: br r31, sys_int_mchk // do a machine check
+
+ lda r17, scb_v_pwrfail(r31) // a1 to interrupt vector
+ mfpr r25, pt_entint
+
+ lda r16, osfint_c_dev(r31) // a0 to device code
+ mtpr r25, exc_addr
+
+ nop // pad exc_addr write
+ nop
+
+ hw_rei_spe
+
+//
+// sys_halt_interrupt
+// A halt interrupt has been detected. Pass control to the console.
+//
+//
+//
+ EXPORT(sys_halt_interrupt)
+
+ ldah r13, 0x1800(r31) // load Halt/^PHalt bits
+ Write_TLINTRSUMx(r13,r10,r14) // clear the ^PHalt bits
+
+ mtpr r11, dtb_cm // Restore Mbox current mode
+ nop
+ nop
+ mtpr r0, pt0
+ lda r0, hlt_c_hw_halt(r31) // set halt code to hw halt
+ br r31, sys_enter_console // enter the console
+
+
+
+//
+// sys_int_mchk_or_crd
+//
+// Current state:
+// Stack is pushed
+// ps, sp and gp are updated
+// r12
+// r13 - INTID (new EV5 IPL)
+// r14 - exc_addr
+// r25 - ISR
+// r16, r17, r18 - available
+//
+//
+ ALIGN_BLOCK
+sys_int_mchk_or_crd:
+ srl r25, isr_v_mck, r12
+ blbs r12, sys_int_mchk
+ //
+ // Not a Machine check interrupt, so must be an Internal CRD interrupt
+ //
+
+ mb //Clear out Cbox prior to reading IPRs
+ srl r25, isr_v_crd, r13 //Check for CRD
+ blbc r13, pal_pal_bug_check_from_int //If CRD not set, shouldn't be here!!!
+
+ lda r9, 1(r31)
+ sll r9, hwint_clr_v_crdc, r9 // get ack bit for crd
+ mtpr r9, ev5__hwint_clr // ack the crd interrupt
+
+ or r31, r31, r12 // clear flag
+ lda r9, mchk_c_ecc_c(r31) // Correctable error MCHK code
+
+sys_merge_sys_corr:
+ ldah r14, 0xfff0(r31)
+ mtpr r0, pt0 // save r0 for scratch
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+ mtpr r1, pt1 // save r0 for scratch
+
+ ldq_p r0, ei_addr(r14) // EI_ADDR IPR
+ ldq_p r10, fill_syn(r14) // FILL_SYN IPR
+ bis r0, r10, r31 // Touch lds to make sure they complete before doing scrub
+
+ blbs r12, 1f // no scrubbing for IRQ0 case
+// XXX bugnion pvc_jsr crd_scrub_mem, bsr=1
+ bsr r13, sys_crd_scrub_mem // and go scrub
+
+ // ld/st pair in scrub routine will have finished due
+ // to ibox stall of stx_c. Don't need another mb.
+ ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
+ or r8, r31, r12 // Must only be executed once in this flow, and must
+ br r31, 2f // be after the scrub routine.
+
+1: ldq_p r8, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
+ // For IRQ0 CRD case only - meaningless data.
+
+2: mfpr r13, pt_mces // Get MCES
+ srl r12, ei_stat_v_ei_es, r14 // Isolate EI_STAT:EI_ES
+ blbc r14, 6f // branch if 630
+ srl r13, mces_v_dsc, r14 // check if 620 reporting disabled
+ blbc r14, 5f // branch if enabled
+ or r13, r31, r14 // don't set SCE if disabled
+ br r31, 8f // continue
+5: bis r13, BIT(mces_v_sce), r14 // Set MCES<SCE> bit
+ br r31, 8f
+
+6: srl r13, mces_v_dpc, r14 // check if 630 reporting disabled
+ blbc r14, 7f // branch if enabled
+ or r13, r31, r14 // don't set PCE if disabled
+ br r31, 8f // continue
+7: bis r13, BIT(mces_v_pce), r14 // Set MCES<PCE> bit
+
+ // Setup SCB if dpc is not set
+8: mtpr r14, pt_mces // Store updated MCES
+ srl r13, mces_v_sce, r1 // Get SCE
+ srl r13, mces_v_pce, r14 // Get PCE
+ or r1, r14, r1 // SCE OR PCE, since they share
+ // the CRD logout frame
+ // Get base of the logout area.
+ GET_IMPURE(r14) // addr of per-cpu impure area
+ GET_ADDR(r14,(pal_logout_area+mchk_crd_base),r14)
+
+ blbc r1, sys_crd_write_logout_frame // If pce/sce not set, build the frame
+
+ // Set the 2nd error flag in the logout area:
+
+ lda r1, 3(r31) // Set retry and 2nd error flags
+ sll r1, 30, r1 // Move to bits 31:30 of logout frame flag longword
+ stl_p r1, mchk_crd_flag+4(r14) // store flag longword
+ br sys_crd_ack
+
+sys_crd_write_logout_frame:
+ // should only be here if neither the pce or sce bits are set
+
+ //
+ // Write the mchk code to the logout area
+ //
+ stq_p r9, mchk_crd_mchk_code(r14)
+
+
+ //
+ // Write the first 2 quadwords of the logout area:
+ //
+ lda r1, 1(r31) // Set retry flag
+ sll r1, 63, r9 // Move retry flag to bit 63
+ lda r1, mchk_crd_size(r9) // Combine retry flag and frame size
+ stq_p r1, mchk_crd_flag(r14) // store flag/frame size
+
+ //
+ // Write error IPRs already fetched to the logout area
+ //
+ stq_p r0, mchk_crd_ei_addr(r14)
+ stq_p r10, mchk_crd_fill_syn(r14)
+ stq_p r8, mchk_crd_ei_stat(r14)
+ stq_p r25, mchk_crd_isr(r14)
+ //
+ // Log system specific info here
+ //
+crd_storeTLEP_:
+ lda r1, 0xffc4(r31) // Get GBUS$MISCR address
+ sll r1, 24, r1
+ ldq_p r1, 0(r1) // Read GBUS$MISCR
+ sll r1, 16, r1 // shift up to proper field
+ mfpr r10, pt_whami // get our node id
+ extbl r10, 1, r10 // shift to bit 0
+ or r1, r10, r1 // merge MISCR and WHAMI
+ stl_p r1, mchk_crd_whami(r14) // write to crd logout area
+ srl r10, 1, r10 // shift off cpu number
+
+ Get_TLSB_Node_Address(r10,r0) // compute our nodespace address
+
+ OSFcrd_TLEPstore_tlsb(tldev)
+ OSFcrd_TLEPstore_tlsb_clr(tlber)
+ OSFcrd_TLEPstore_tlsb_clr(tlesr0)
+ OSFcrd_TLEPstore_tlsb_clr(tlesr1)
+ OSFcrd_TLEPstore_tlsb_clr(tlesr2)
+ OSFcrd_TLEPstore_tlsb_clr(tlesr3)
+
+sys_crd_ack:
+ mfpr r0, pt0 // restore r0
+ mfpr r1, pt1 // restore r1
+
+ srl r12, ei_stat_v_ei_es, r12
+ blbc r12, 5f
+ srl r13, mces_v_dsc, r10 // logging enabled?
+ br r31, 6f
+5: srl r13, mces_v_dpc, r10 // logging enabled?
+6: blbc r10, sys_crd_post_interrupt // logging enabled -- report it
+
+ // logging not enabled
+ // Get base of the logout area.
+ GET_IMPURE(r13) // addr of per-cpu impure area
+ GET_ADDR(r13,(pal_logout_area+mchk_crd_base),r13)
+ ldl_p r10, mchk_crd_rsvd(r13) // bump counter
+ addl r10, 1, r10
+ stl_p r10, mchk_crd_rsvd(r13)
+ mb
+ br r31, sys_crd_dismiss_interrupt // just return
+
+ //
+ // The stack is pushed. Load up a0,a1,a2 and vector via entInt
+ //
+ //
+
+ ALIGN_BRANCH
+sys_crd_post_interrupt:
+ lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
+ lda r17, scb_v_proc_corr_err(r31) // a1 <- interrupt vector
+
+ blbc r12, 1f
+ lda r17, scb_v_sys_corr_err(r31) // a1 <- interrupt vector
+
+1: subq r31, 1, r18 // get a -1
+ mfpr r25, pt_entInt
+
+ srl r18, 42, r18 // shift off low bits of kseg addr
+ mtpr r25, exc_addr // load interrupt vector
+
+ sll r18, 42, r18 // shift back into position
+ or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
+
+ hw_rei_spe // done
+
+
+ //
+ // The stack is pushed. Need to back out of it all.
+ //
+
+sys_crd_dismiss_interrupt:
+ br r31, Call_Pal_Rti
+
+
+// sys_crd_scrub_mem
+//
+// r0 = addr of cache block
+//
+ ALIGN_BLOCK // align for branch target
+sys_crd_scrub_mem:
+ // now find error in memory, and attempt to scrub that cache block
+ // This routine just scrubs the failing octaword
+ // Only need to "touch" one quadword per octaword to accomplish the scrub
+ srl r0, 39, r8 // get high bit of bad pa
+ blbs r8, 1f // don't attempt fixup on IO space addrs
+ nop // needed to align the ldq_pl to octaword boundary
+ nop // "
+
+ ldq_p r8, 0(r0) // attempt to read the bad memory
+ // location
+ // (Note bits 63:40,3:0 of ei_addr
+ // are set to 1, but as long as
+ // we are doing a phys ref, should
+ // be ok)
+ nop // Needed to keep the Ibox from swapping the ldq_p into E1
+
+ stq_p r8, 0(r0) // Store it back if it is still there.
+ // If store fails, location already
+ // scrubbed by someone else
+
+ nop // needed to align the ldq_p to octaword boundary
+
+ lda r8, 0x20(r31) // flip bit 5 to touch next hexaword
+ xor r8, r0, r0
+ nop // needed to align the ldq_p to octaword boundary
+ nop // "
+
+ ldq_p r8, 0(r0) // attempt to read the bad memory
+ // location
+ // (Note bits 63:40,3:0 of ei_addr
+ // are set to 1, but as long as
+ // we are doing a phys ref, should
+ // be ok)
+ nop // Needed to keep the Ibox from swapping the ldq_p into E1
+
+ stq_p r8, 0(r0) // Store it back if it is still there.
+ // If store fails, location already
+ // scrubbed by someone else
+
+ lda r8, 0x20(r31) // restore r0 to original address
+ xor r8, r0, r0
+
+ //at this point, ei_stat could be locked due to a new corr error on the ld,
+ //so read ei_stat to unlock AFTER this routine.
+
+// XXX bugnion pvc$jsr crd_scrub_mem, bsr=1, dest=1
+1: ret r31, (r13) // and back we go
+
+
+//
+// sys_int_mchk - MCHK Interrupt code
+//
+// Machine check interrupt from the system. Setup and join the
+// regular machine check flow.
+// On exit:
+// pt0 - saved r0
+// pt1 - saved r1
+// pt4 - saved r4
+// pt5 - saved r5
+// pt6 - saved r6
+// pt10 - saved exc_addr
+// pt_misc<47:32> - mchk code
+// pt_misc<31:16> - scb vector
+// r14 - base of Cbox IPRs in IO space
+// MCES<mchk> is set
+//
+ ALIGN_BLOCK
+sys_int_mchk:
+ lda r14, mchk_c_sys_hrd_error(r31)
+ mfpr r12, exc_addr
+
+ addq r14, 1, r14 // Flag as interrupt
+ nop
+
+ sll r14, 32, r14 // Move mchk code to position
+ mtpr r12, pt10 // Stash exc_addr
+
+ mfpr r12, pt_misc // Get MCES and scratch
+ mtpr r0, pt0 // Stash for scratch
+
+ zap r12, 0x3c, r12 // Clear scratch
+ blbs r12, sys_double_machine_check // MCHK halt if double machine check
+
+ or r12, r14, r12 // Combine mchk code
+ lda r14, scb_v_sysmchk(r31) // Get SCB vector
+
+ sll r14, 16, r14 // Move SCBv to position
+ or r12, r14, r14 // Combine SCBv
+
+ bis r14, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
+ mtpr r14, pt_misc // Save mchk code!scbv!whami!mces
+
+ ldah r14, 0xfff0(r31)
+ mtpr r1, pt1 // Stash for scratch
+
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+ mtpr r4, pt4
+
+ mtpr r5, pt5
+
+ mtpr r6, pt6
+ br r31, sys_mchk_collect_iprs // Join common machine check flow
+
+
+//
+// sys_int_perf_cnt - Performance counter interrupt code
+//
+// A performance counter interrupt has been detected. The stack
+// has been pushed. IPL and PS are updated as well.
+//
+// on exit to interrupt entry point ENTINT::
+// a0 = osfint$c_perf
+// a1 = scb$v_perfmon (650)
+// a2 = 0 if performance counter 0 fired
+// a2 = 1 if performance counter 1 fired
+// a2 = 2 if performance counter 2 fired
+// (if more than one counter overflowed, an interrupt will be
+// generated for each counter that overflows)
+//
+//
+//
+ ALIGN_BLOCK
+sys_int_perf_cnt: // Performance counter interrupt
+ lda r17, scb_v_perfmon(r31) // a1 to interrupt vector
+ mfpr r25, pt_entint
+
+ lda r16, osfint_c_perf(r31) // a0 to perf counter code
+ mtpr r25, exc_addr
+
+ //isolate which perf ctr fired, load code in a2, and ack
+ mfpr r25, isr
+ or r31, r31, r18 // assume interrupt was pc0
+
+ srl r25, isr_v_pc1, r25 // isolate
+ cmovlbs r25, 1, r18 // if pc1 set, load 1 into r14
+
+ srl r25, 1, r25 // get pc2
+ cmovlbs r25, 2, r18 // if pc2 set, load 2 into r14
+
+ lda r25, 1(r31) // get a one
+ sll r25, r18, r25
+
+ sll r25, hwint_clr_v_pc0c, r25 // ack only the perf counter that generated the interrupt
+ mtpr r25, hwint_clr
+
+ hw_rei_spe
+
+
+
+//
+// sys_reset - System specific RESET code
+// On entry:
+// r1 = pal_base +8
+//
+// Entry state on trap:
+// r0 = whami
+// r2 = base of scratch area
+// r3 = halt code
+// and the following 3 if init_cbox is enabled:
+// r5 = sc_ctl
+// r6 = bc_ctl
+// r7 = bc_cnfg
+//
+// Entry state on switch:
+// r17 - new PC
+// r18 - new PCBB
+// r19 - new VPTB
+//
+
+ ALIGN_BLOCK
+ .globl sys_reset
+sys_reset:
+// mtpr r31, ic_flush_ctl // do not flush the icache - done by hardware before SROM load
+ mtpr r31, itb_ia // clear the ITB
+ mtpr r31, dtb_ia // clear the DTB
+
+ lda r1, -8(r1) // point to start of code
+ mtpr r1, pal_base // initialize PAL_BASE
+
+ // Interrupts
+ mtpr r31, astrr // stop ASTs
+ mtpr r31, aster // stop ASTs
+ mtpr r31, sirr // clear software interrupts
+
+ mtpr r0, pt1 // r0 is whami (unless we entered via swp)
+
+ ldah r1,(BIT(icsr_v_sde-16)|BIT(icsr_v_fpe-16)|BIT(icsr_v_spe-16+1))(zero)
+
+ bis r31, 1, r0
+ sll r0, icsr_v_crde, r0 // A 1 in iscr<corr_read_enable>
+ or r0, r1, r1 // Set the bit
+
+ mtpr r1, icsr // ICSR - Shadows enabled, Floating point enable,
+ // super page enabled, correct read per assembly option
+
+ // Mbox/Dcache init
+ lda r1,BIT(mcsr_v_sp1)(zero)
+
+ mtpr r1, mcsr // MCSR - Super page enabled
+ lda r1, BIT(dc_mode_v_dc_ena)(r31)
+ ALIGN_BRANCH
+// mtpr r1, dc_mode // turn Dcache on
+ nop
+
+ mfpr r31, pt0 // No Mbox instr in 1,2,3,4
+ mfpr r31, pt0
+ mfpr r31, pt0
+ mfpr r31, pt0
+ mtpr r31, dc_flush // flush Dcache
+
+ // build PS (IPL=7,CM=K,VMM=0,SW=0)
+ lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7
+ lda r1, 0x1F(r31)
+ mtpr r1, ipl // set internal <ipl>=1F
+ mtpr r31, ev5__ps // set new ps<cm>=0, Ibox copy
+ mtpr r31, dtb_cm // set new ps<cm>=0, Mbox copy
+
+ // Create the PALtemp pt_intmask
+ // MAP:
+ // OSF IPL EV5 internal IPL(hex) note
+ // 0 0
+ // 1 1
+ // 2 2
+ // 3 14 device
+ // 4 15 device
+ // 5 16 device
+ // 6 1E device,performance counter, powerfail
+ // 7 1F
+ //
+
+ ldah r1, 0x1f1E(r31) // Create upper lw of int_mask
+ lda r1, 0x1615(r1)
+
+ sll r1, 32, r1
+ ldah r1, 0x1402(r1) // Create lower lw of int_mask
+
+ lda r1, 0x0100(r1)
+ mtpr r1, pt_intmask // Stash in PALtemp
+
+ // Unlock a bunch of chip internal IPRs
+ mtpr r31, exc_sum // clear out exeception summary and exc_mask
+ mfpr r31, va // unlock va, mmstat
+ lda r8,(BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(zero)
+
+ mtpr r8, icperr_stat // Clear Icache parity error & timeout status
+ lda r8,(BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
+
+ mtpr r8, dcperr_stat // Clear Dcache parity error status
+
+ rc r0 // clear intr_flag
+ mtpr r31, pt_trap
+
+ mfpr r0, pt_misc
+ srl r0, pt_misc_v_switch, r1
+ blbs r1, sys_reset_switch // see if we got here from swppal
+
+ // Rest of the "real" reset flow
+ // ASN
+ mtpr r31, dtb_asn
+ mtpr r31, itb_asn
+
+ lda r1, 0x67(r31)
+ sll r1, hwint_clr_v_pc0c, r1
+ mtpr r1, hwint_clr // Clear hardware interrupt requests
+
+ lda r1, BIT(mces_v_dpc)(r31) // 1 in disable processor correctable error
+ mfpr r0, pt1 // get whami
+ insbl r0, 1, r0 // isolate whami in correct pt_misc position
+ or r0, r1, r1 // combine whami and mces
+ mtpr r1, pt_misc // store whami and mces, swap bit clear
+
+ zapnot r3, 1, r0 // isolate halt code
+ mtpr r0, pt0 // save entry type
+
+ // Cycle counter
+ or r31, 1, r9 // get a one
+ sll r9, 32, r9 // shift to <32>
+ mtpr r31, cc // clear Cycle Counter
+ mtpr r9, cc_ctl // clear and enable the Cycle Counter
+ mtpr r31, pt_scc // clear System Cycle Counter
+
+
+ // Misc PALtemps
+ mtpr r31, maf_mode // no mbox instructions for 3 cycles
+ or r31, 1, r1 // get bogus scbb value
+ mtpr r1, pt_scbb // load scbb
+ mtpr r31, pt_prbr // clear out prbr
+#if defined(TSUNAMI) || defined(BIG_TSUNAMI)
+ // yes, this is ugly, but you figure out a better
+ // way to get the address of the kludge_initial_pcbb
+ // in r1 with an uncooperative assembler --ali
+ br r1, kludge_getpcb_addr
+ br r31, kludge_initial_pcbb
+kludge_getpcb_addr:
+ ldq_p r19, 0(r1)
+ sll r19, 44, r19
+ srl r19, 44, r19
+ mulq r19,4,r19
+ addq r19, r1, r1
+ addq r1,4,r1
+#elif defined(TLASER)
+ // or zero,kludge_initial_pcbb,r1
+ GET_ADDR(r1, (kludge_initial_pcbb-pal_base), r1)
+#endif
+ mtpr r1, pt_pcbb // load pcbb
+ lda r1, 2(r31) // get a two
+ sll r1, 32, r1 // gen up upper bits
+ mtpr r1, mvptbr
+ mtpr r1, ivptbr
+ mtpr r31, pt_ptbr
+ // Performance counters
+ mtpr r31, pmctr
+
+ // Clear pmctr_ctl in impure area
+
+
+ ldah r14, 0xfff0(r31)
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+ GET_IMPURE(r13)
+ stq_p r31, 0(r13) // Clear lock_flag
+
+ mfpr r0, pt0 // get entry type
+ br r31, sys_enter_console // enter the cosole
+
+
+ // swppal entry
+ // r0 - pt_misc
+ // r17 - new PC
+ // r18 - new PCBB
+ // r19 - new VPTB
+sys_reset_switch:
+ or r31, 1, r9
+ sll r9, pt_misc_v_switch, r9
+ bic r0, r9, r0 // clear switch bit
+ mtpr r0, pt_misc
+
+ rpcc r1 // get cyccounter
+
+ ldq_p r22, osfpcb_q_fen(r18) // get new fen/pme
+ ldl_p r23, osfpcb_l_cc(r18) // get cycle counter
+ ldl_p r24, osfpcb_l_asn(r18) // get new asn
+
+
+ ldq_p r25, osfpcb_q_Mmptr(r18)// get new mmptr
+ sll r25, page_offset_size_bits, r25 // convert pfn to pa
+ mtpr r25, pt_ptbr // load the new mmptr
+ mtpr r18, pt_pcbb // set new pcbb
+
+ bic r17, 3, r17 // clean use pc
+ mtpr r17, exc_addr // set new pc
+ mtpr r19, mvptbr
+ mtpr r19, ivptbr
+
+ ldq_p r30, osfpcb_q_Usp(r18) // get new usp
+ mtpr r30, pt_usp // save usp
+
+ sll r24, dtb_asn_v_asn, r8
+ mtpr r8, dtb_asn
+ sll r24, itb_asn_v_asn, r24
+ mtpr r24, itb_asn
+
+ mfpr r25, icsr // get current icsr
+ lda r24, 1(r31)
+ sll r24, icsr_v_fpe, r24 // 1 in icsr<fpe> position
+ bic r25, r24, r25 // clean out old fpe
+ and r22, 1, r22 // isolate new fen bit
+ sll r22, icsr_v_fpe, r22
+ or r22, r25, r25 // or in new fpe
+ mtpr r25, icsr // update ibox ipr
+
+ subl r23, r1, r1 // gen new cc offset
+ insll r1, 4, r1 // << 32
+ mtpr r1, cc // set new offset
+
+ or r31, r31, r0 // set success
+ ldq_p r30, osfpcb_q_Ksp(r18) // get new ksp
+ mfpr r31, pt0 // stall
+ hw_rei_stall
+
+//
+//sys_machine_check - Machine check PAL
+// A machine_check trap has occurred. The Icache has been flushed.
+//
+//
+
+ ALIGN_BLOCK
+EXPORT(sys_machine_check)
+ // Need to fill up the refill buffer (32 instructions) and
+ // then flush the Icache again.
+ // Also, due to possible 2nd Cbox register file write for
+ // uncorrectable errors, no register file read or write for 7 cycles.
+
+ //nop
+ .long 0x4000054 // call M5 Panic
+ mtpr r0, pt0 // Stash for scratch -- OK if Cbox overwrites
+ // r0 later
+ nop
+ nop
+
+ nop
+ nop
+
+ nop
+ nop
+
+ nop
+ nop
+ // 10 instructions// 5 cycles
+
+ nop
+ nop
+
+ nop
+ nop
+
+ // Register file can now be written
+ lda r0, scb_v_procmchk(r31) // SCB vector
+ mfpr r13, pt_mces // Get MCES
+ sll r0, 16, r0 // Move SCBv to correct position
+ bis r13, BIT(mces_v_mchk), r14 // Set MCES<MCHK> bit
+
+
+ zap r14, 0x3C, r14 // Clear mchk_code word and SCBv word
+ mtpr r14, pt_mces
+ // 20 instructions
+
+ nop
+ or r14, r0, r14 // Insert new SCB vector
+ lda r0, mchk_c_proc_hrd_error(r31) // MCHK code
+ mfpr r12, exc_addr
+
+ sll r0, 32, r0 // Move MCHK code to correct position
+ mtpr r4, pt4
+ or r14, r0, r14 // Insert new MCHK code
+ mtpr r14, pt_misc // Store updated MCES, MCHK code, and SCBv
+
+ ldah r14, 0xfff0(r31)
+ mtpr r1, pt1 // Stash for scratch - 30 instructions
+
+ zap r14, 0xE0, r14 // Get Cbox IPR base
+ mtpr r12, pt10 // Stash exc_addr
+
+
+
+ mtpr r31, ic_flush_ctl // Second Icache flush, now it is really flushed.
+ blbs r13, sys_double_machine_check // MCHK halt if double machine check
+
+ mtpr r6, pt6
+ mtpr r5, pt5
+
+ // Look for the powerfail cases here....
+ mfpr r4, isr
+ srl r4, isr_v_pfl, r4
+ blbc r4, sys_mchk_collect_iprs // skip if no powerfail interrupt pending
+ lda r4, 0xffc4(r31) // get GBUS$MISCR address bits
+ sll r4, 24, r4 // shift to proper position
+ ldq_p r4, 0(r4) // read GBUS$MISCR
+ srl r4, 5, r4 // isolate bit <5>
+ blbc r4, sys_mchk_collect_iprs // skip if already cleared
+ // No missed CFAIL mchk
+ lda r5, 0xffc7(r31) // get GBUS$SERNUM address bits
+ sll r5, 24, r5 // shift to proper position
+ lda r6, 0x40(r31) // get bit <6> mask
+ ldq_p r4, 0(r5) // read GBUS$SERNUM
+ or r4, r6, r6 // set bit <6>
+ stq_p r6, 0(r5) // clear GBUS$SERNUM<6>
+ mb
+ mb
+
+
+ //
+ // Start to collect the IPRs. Common entry point for mchk flows.
+ //
+ // Current state:
+ // pt0 - saved r0
+ // pt1 - saved r1
+ // pt4 - saved r4
+ // pt5 - saved r5
+ // pt6 - saved r6
+ // pt10 - saved exc_addr
+ // pt_misc<47:32> - mchk code
+ // pt_misc<31:16> - scb vector
+ // r14 - base of Cbox IPRs in IO space
+ // r0, r1, r4, r5, r6, r12, r13, r25 - available
+ // r8, r9, r10 - available as all loads are physical
+ // MCES<mchk> is set
+ //
+ //
+
+EXPORT(sys_mchk_collect_iprs)
+ .long 0x4000054 // call M5 Panic
+ //mb // MB before reading Scache IPRs
+ mfpr r1, icperr_stat
+
+ mfpr r8, dcperr_stat
+ mtpr r31, dc_flush // Flush the Dcache
+
+ mfpr r31, pt0 // Pad Mbox instructions from dc_flush
+ mfpr r31, pt0
+ nop
+ nop
+
+ ldq_p r9, sc_addr(r14) // SC_ADDR IPR
+ bis r9, r31, r31 // Touch ld to make sure it completes before
+ // read of SC_STAT
+ ldq_p r10, sc_stat(r14) // SC_STAT, also unlocks SC_ADDR
+
+ ldq_p r12, ei_addr(r14) // EI_ADDR IPR
+ ldq_p r13, bc_tag_addr(r14) // BC_TAG_ADDR IPR
+ ldq_p r0, fill_syn(r14) // FILL_SYN IPR
+ bis r12, r13, r31 // Touch lds to make sure they complete before reading EI_STAT
+ bis r0, r0, r31 // Touch lds to make sure they complete before reading EI_STAT
+ ldq_p r25, ei_stat(r14) // EI_STAT, unlock EI_ADDR, BC_TAG_ADDR, FILL_SYN
+ ldq_p r31, ei_stat(r14) // Read again to insure it is unlocked
+
+
+
+
+ //
+ // Look for nonretryable cases
+ // In this segment:
+ // r5<0> = 1 means retryable
+ // r4, r6, and r14 are available for scratch
+ //
+ //
+
+
+ bis r31, r31, r5 // Clear local retryable flag
+ srl r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits to low bits
+
+ lda r4, 1(r31)
+ sll r4, icperr_stat_v_tmr, r4
+ and r1, r4, r4 // Timeout reset
+ bne r4, sys_cpu_mchk_not_retryable
+
+ and r8, BIT(dcperr_stat_v_lock), r4 // DCache parity error locked
+ bne r4, sys_cpu_mchk_not_retryable
+
+ lda r4, 1(r31)
+ sll r4, sc_stat_v_sc_scnd_err, r4
+ and r10, r4, r4 // 2nd Scache error occurred
+ bne r4, sys_cpu_mchk_not_retryable
+
+
+ bis r31, 0xa3, r4 // EI_STAT Bcache Tag Parity Error, Bcache Tag Control
+ // Parity Error, Interface Parity Error, 2nd Error
+
+ and r25, r4, r4
+ bne r4, sys_cpu_mchk_not_retryable
+
+// bis r31, #<1@<ei_stat$v_unc_ecc_err-ei_stat$v_bc_tperr>>, r4
+ bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
+ and r25, r4, r4 // Isolate the Uncorrectable Error Bit
+// bis r31, #<1@<ei_stat$v_fil_ird-ei_stat$v_bc_tperr>>, r6
+ bis r31, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r6 // Isolate the Iread bit
+ cmovne r6, 0, r4 // r4 = 0 if IRD or if No Uncorrectable Error
+ bne r4, sys_cpu_mchk_not_retryable
+
+ lda r4, 7(r31)
+ and r10, r4, r4 // Isolate the Scache Tag Parity Error bits
+ bne r4, sys_cpu_mchk_not_retryable // All Scache Tag PEs are not retryable
+
+
+ lda r4, 0x7f8(r31)
+ and r10, r4, r4 // Isolate the Scache Data Parity Error bits
+ srl r10, sc_stat_v_cbox_cmd, r6
+ and r6, 0x1f, r6 // Isolate Scache Command field
+ subq r6, 1, r6 // Scache Iread command = 1
+ cmoveq r6, 0, r4 // r4 = 0 if IRD or if No Parity Error
+ bne r4, sys_cpu_mchk_not_retryable
+
+ // Look for the system unretryable cases here....
+
+ mfpr r4, isr // mchk_interrupt pin asserted
+ srl r4, isr_v_mck, r4
+ blbs r4, sys_cpu_mchk_not_retryable
+
+
+
+ //
+ // Look for retryable cases
+ // In this segment:
+ // r5<0> = 1 means retryable
+ // r6 - holds the mchk code
+ // r4 and r14 are available for scratch
+ //
+ //
+
+
+ // Within the chip, the retryable cases are Istream errors
+ lda r4, 3(r31)
+ sll r4, icperr_stat_v_dpe, r4
+ and r1, r4, r4
+ cmovne r4, 1, r5 // Retryable if just Icache parity error
+
+
+ lda r4, 0x7f8(r31)
+ and r10, r4, r4 // Isolate the Scache Data Parity Error bits
+ srl r10, sc_stat_v_cbox_cmd, r14
+ and r14, 0x1f, r14 // Isolate Scache Command field
+ subq r14, 1, r14 // Scache Iread command = 1
+ cmovne r4, 1, r4 // r4 = 1 if Scache data parity error bit set
+ cmovne r14, 0, r4 // r4 = 1 if Scache PE and Iread
+ bis r4, r5, r5 // Accumulate
+
+
+ bis r31, BIT((ei_stat_v_unc_ecc_err-ei_stat_v_bc_tperr)), r4
+ and r25, r4, r4 // Isolate the Uncorrectable Error Bit
+ and r25, BIT((ei_stat_v_fil_ird-ei_stat_v_bc_tperr)), r14 // Isolate the Iread bit
+ cmovne r4, 1, r4 // r4 = 1 if uncorr error
+ cmoveq r14, 0, r4 // r4 = 1 if uncorr and Iread
+ bis r4, r5, r5 // Accumulate
+
+ mfpr r6, pt_misc
+ extwl r6, 4, r6 // Fetch mchk code
+ bic r6, 1, r6 // Clear flag from interrupt flow
+ cmovne r5, mchk_c_retryable_ird, r6 // Set mchk code
+
+
+ //
+ // Write the logout frame
+ //
+ // Current state:
+ // r0 - fill_syn
+ // r1 - icperr_stat
+ // r4 - available
+ // r5<0> - retry flag
+ // r6 - mchk code
+ // r8 - dcperr_stat
+ // r9 - sc_addr
+ // r10 - sc_stat
+ // r12 - ei_addr
+ // r13 - bc_tag_addr
+ // r14 - available
+ // r25 - ei_stat (shifted)
+ // pt0 - saved r0
+ // pt1 - saved r1
+ // pt4 - saved r4
+ // pt5 - saved r5
+ // pt6 - saved r6
+ // pt10 - saved exc_addr
+ //
+ //
+
+sys_mchk_write_logout_frame:
+ // Get base of the logout area.
+ GET_IMPURE(r14) // addr of per-cpu impure area
+ GET_ADDR(r14,pal_logout_area+mchk_mchk_base,r14)
+
+ // Write the first 2 quadwords of the logout area:
+
+ sll r5, 63, r5 // Move retry flag to bit 63
+ lda r4, mchk_size(r5) // Combine retry flag and frame size
+ stq_p r4, mchk_flag(r14) // store flag/frame size
+ lda r4, mchk_sys_base(r31) // sys offset
+ sll r4, 32, r4
+ lda r4, mchk_cpu_base(r4) // cpu offset
+ stq_p r4, mchk_offsets(r14) // store sys offset/cpu offset into logout frame
+
+ //
+ // Write the mchk code to the logout area
+ // Write error IPRs already fetched to the logout area
+ // Restore some GPRs from PALtemps
+ //
+
+ mfpr r5, pt5
+ stq_p r6, mchk_mchk_code(r14)
+ mfpr r4, pt4
+ stq_p r1, mchk_ic_perr_stat(r14)
+ mfpr r6, pt6
+ stq_p r8, mchk_dc_perr_stat(r14)
+ mfpr r1, pt1
+ stq_p r9, mchk_sc_addr(r14)
+ stq_p r10, mchk_sc_stat(r14)
+ stq_p r12, mchk_ei_addr(r14)
+ stq_p r13, mchk_bc_tag_addr(r14)
+ stq_p r0, mchk_fill_syn(r14)
+ mfpr r0, pt0
+ sll r25, ei_stat_v_bc_tperr, r25 // Move EI_STAT status bits back to expected position
+ // retrieve lower 28 bits again from ei_stat and restore before storing to logout frame
+ ldah r13, 0xfff0(r31)
+ zapnot r13, 0x1f, r13
+ ldq_p r13, ei_stat(r13)
+ sll r13, 64-ei_stat_v_bc_tperr, r13
+ srl r13, 64-ei_stat_v_bc_tperr, r13
+ or r25, r13, r25
+ stq_p r25, mchk_ei_stat(r14)
+
+
+
+
+ //
+ // complete the CPU-specific part of the logout frame
+ //
+
+ ldah r13, 0xfff0(r31)
+ zap r13, 0xE0, r13 // Get Cbox IPR base
+ ldq_p r13, ld_lock(r13) // Get ld_lock IPR
+ stq_p r13, mchk_ld_lock(r14) // and stash it in the frame
+
+ // Unlock IPRs
+ lda r8, (BIT(dcperr_stat_v_lock)|BIT(dcperr_stat_v_seo))(r31)
+ mtpr r8, dcperr_stat // Clear Dcache parity error status
+
+ lda r8, (BIT(icperr_stat_v_dpe)|BIT(icperr_stat_v_tpe)|BIT(icperr_stat_v_tmr))(r31)
+ mtpr r8, icperr_stat // Clear Icache parity error & timeout status
+
+1: ldq_p r8, mchk_ic_perr_stat(r14) // get ICPERR_STAT value
+ GET_ADDR(r0,0x1800,r31) // get ICPERR_STAT value
+ and r0, r8, r0 // compare
+ beq r0, 2f // check next case if nothing set
+ lda r0, mchk_c_retryable_ird(r31) // set new MCHK code
+ br r31, do_670 // setup new vector
+
+2: ldq_p r8, mchk_dc_perr_stat(r14) // get DCPERR_STAT value
+ GET_ADDR(r0,0x3f,r31) // get DCPERR_STAT value
+ and r0, r8, r0 // compare
+ beq r0, 3f // check next case if nothing set
+ lda r0, mchk_c_dcperr(r31) // set new MCHK code
+ br r31, do_670 // setup new vector
+
+3: ldq_p r8, mchk_sc_stat(r14) // get SC_STAT value
+ GET_ADDR(r0,0x107ff,r31) // get SC_STAT value
+ and r0, r8, r0 // compare
+ beq r0, 4f // check next case if nothing set
+ lda r0, mchk_c_scperr(r31) // set new MCHK code
+ br r31, do_670 // setup new vector
+
+4: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value
+ GET_ADDR(r0,0x30000000,r31) // get EI_STAT value
+ and r0, r8, r0 // compare
+ beq r0, 5f // check next case if nothing set
+ lda r0, mchk_c_bcperr(r31) // set new MCHK code
+ br r31, do_670 // setup new vector
+
+5: ldl_p r8, mchk_tlber(r14) // get TLBER value
+ GET_ADDR(r0,0xfe01,r31) // get high TLBER mask value
+ sll r0, 16, r0 // shift into proper position
+ GET_ADDR(r1,0x03ff,r31) // get low TLBER mask value
+ or r0, r1, r0 // merge mask values
+ and r0, r8, r0 // compare
+ beq r0, 6f // check next case if nothing set
+ GET_ADDR(r0, 0xfff0, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+6: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value
+ GET_ADDR(r0,0xff7f,r31) // get TLEPAERR mask value
+ and r0, r8, r0 // compare
+ beq r0, 7f // check next case if nothing set
+ GET_ADDR(r0, 0xfffa, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+7: ldl_p r8, mchk_tlepderr(r14) // get TLEPDERR value
+ GET_ADDR(r0,0x7,r31) // get TLEPDERR mask value
+ and r0, r8, r0 // compare
+ beq r0, 8f // check next case if nothing set
+ GET_ADDR(r0, 0xfffb, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+8: ldl_p r8, mchk_tlepmerr(r14) // get TLEPMERR value
+ GET_ADDR(r0,0x3f,r31) // get TLEPMERR mask value
+ and r0, r8, r0 // compare
+ beq r0, 9f // check next case if nothing set
+ GET_ADDR(r0, 0xfffc, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+9: ldq_p r8, mchk_ei_stat(r14) // get EI_STAT value
+ GET_ADDR(r0,0xb,r31) // get EI_STAT mask value
+ sll r0, 32, r0 // shift to upper lw
+ and r0, r8, r0 // compare
+ beq r0, 1f // check next case if nothing set
+ GET_ADDR(r0,0xfffd,r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+1: ldl_p r8, mchk_tlepaerr(r14) // get TLEPAERR value
+ GET_ADDR(r0,0x80,r31) // get TLEPAERR mask value
+ and r0, r8, r0 // compare
+ beq r0, cont_logout_frame // check next case if nothing set
+ GET_ADDR(r0, 0xfffe, r31) // set new MCHK code
+ br r31, do_660 // setup new vector
+
+do_670: lda r8, scb_v_procmchk(r31) // SCB vector
+ br r31, do_6x0_cont
+do_660: lda r8, scb_v_sysmchk(r31) // SCB vector
+do_6x0_cont:
+ sll r8, 16, r8 // shift to proper position
+ mfpr r1, pt_misc // fetch current pt_misc
+ GET_ADDR(r4,0xffff, r31) // mask for vector field
+ sll r4, 16, r4 // shift to proper position
+ bic r1, r4, r1 // clear out old vector field
+ or r1, r8, r1 // merge in new vector
+ mtpr r1, pt_misc // save new vector field
+ stl_p r0, mchk_mchk_code(r14) // save new mchk code
+
+cont_logout_frame:
+ // Restore some GPRs from PALtemps
+ mfpr r0, pt0
+ mfpr r1, pt1
+ mfpr r4, pt4
+
+ mfpr r12, pt10 // fetch original PC
+ blbs r12, sys_machine_check_while_in_pal // MCHK halt if machine check in pal
+
+//XXXbugnion pvc_jsr armc, bsr=1
+ bsr r12, sys_arith_and_mchk // go check for and deal with arith trap
+
+ mtpr r31, exc_sum // Clear Exception Summary
+
+ mfpr r25, pt10 // write exc_addr after arith_and_mchk to pickup new pc
+ stq_p r25, mchk_exc_addr(r14)
+
+ //
+ // Set up the km trap
+ //
+
+
+sys_post_mchk_trap:
+ mfpr r25, pt_misc // Check for flag from mchk interrupt
+ extwl r25, 4, r25
+ blbs r25, sys_mchk_stack_done // Stack from already pushed if from interrupt flow
+
+ bis r14, r31, r12 // stash pointer to logout area
+ mfpr r14, pt10 // get exc_addr
+
+ sll r11, 63-3, r25 // get mode to msb
+ bge r25, 3f
+
+ mtpr r31, dtb_cm
+ mtpr r31, ev5__ps
+
+ mtpr r30, pt_usp // save user stack
+ mfpr r30, pt_ksp
+
+3:
+ lda sp, 0-osfsf_c_size(sp) // allocate stack space
+ nop
+
+ stq r18, osfsf_a2(sp) // a2
+ stq r11, osfsf_ps(sp) // save ps
+
+ stq r14, osfsf_pc(sp) // save pc
+ mfpr r25, pt_entint // get the VA of the interrupt routine
+
+ stq r16, osfsf_a0(sp) // a0
+ lda r16, osfint_c_mchk(r31) // flag as mchk in a0
+
+ stq r17, osfsf_a1(sp) // a1
+ mfpr r17, pt_misc // get vector
+
+ stq r29, osfsf_gp(sp) // old gp
+ mtpr r25, exc_addr //
+
+ or r31, 7, r11 // get new ps (km, high ipl)
+ subq r31, 1, r18 // get a -1
+
+ extwl r17, 2, r17 // a1 <- interrupt vector
+ bis r31, ipl_machine_check, r25
+
+ mtpr r25, ipl // Set internal ipl
+ srl r18, 42, r18 // shift off low bits of kseg addr
+
+ sll r18, 42, r18 // shift back into position
+ mfpr r29, pt_kgp // get the kern r29
+
+ or r12, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
+ hw_rei_spe // out to interrupt dispatch routine
+
+
+ //
+ // The stack is pushed. Load up a0,a1,a2 and vector via entInt
+ //
+ //
+ ALIGN_BRANCH
+sys_mchk_stack_done:
+ lda r16, osfint_c_mchk(r31) // flag as mchk/crd in a0
+ lda r17, scb_v_sysmchk(r31) // a1 <- interrupt vector
+
+ subq r31, 1, r18 // get a -1
+ mfpr r25, pt_entInt
+
+ srl r18, 42, r18 // shift off low bits of kseg addr
+ mtpr r25, exc_addr // load interrupt vector
+
+ sll r18, 42, r18 // shift back into position
+ or r14, r18, r18 // EV4 algorithm - pass pointer to mchk frame as kseg address
+
+ hw_rei_spe // done
+
+
+ ALIGN_BRANCH
+sys_cpu_mchk_not_retryable:
+ mfpr r6, pt_misc
+ extwl r6, 4, r6 // Fetch mchk code
+ br r31, sys_mchk_write_logout_frame //
+
+
+
+//
+//sys_double_machine_check - a machine check was started, but MCES<MCHK> was
+// already set. We will now double machine check halt.
+//
+// pt0 - old R0
+//
+//
+
+EXPORT(sys_double_machine_check)
+ lda r0, hlt_c_dbl_mchk(r31)
+ br r31, sys_enter_console
+
+//
+// sys_machine_check_while_in_pal - a machine check was started,
+// exc_addr points to a PAL PC. We will now machine check halt.
+//
+// pt0 - old R0
+//
+//
+sys_machine_check_while_in_pal:
+ stq_p r12, mchk_exc_addr(r14) // exc_addr has not yet been written
+ lda r0, hlt_c_mchk_from_pal(r31)
+ br r31, sys_enter_console
+
+
+//ARITH and MCHK
+// Check for arithmetic errors and build trap frame,
+// but don't post the trap.
+// on entry:
+// pt10 - exc_addr
+// r12 - return address
+// r14 - logout frame pointer
+// r13 - available
+// r8,r9,r10 - available except across stq's
+// pt0,1,6 - available
+//
+// on exit:
+// pt10 - new exc_addr
+// r17 = exc_mask
+// r16 = exc_sum
+// r14 - logout frame pointer
+//
+ ALIGN_BRANCH
+sys_arith_and_mchk:
+ mfpr r13, ev5__exc_sum
+ srl r13, exc_sum_v_swc, r13
+ bne r13, handle_arith_and_mchk
+
+// XXX bugnion pvc$jsr armc, bsr=1, dest=1
+ ret r31, (r12) // return if no outstanding arithmetic error
+
+handle_arith_and_mchk:
+ mtpr r31, ev5__dtb_cm // Set Mbox current mode to kernel
+ // no virt ref for next 2 cycles
+ mtpr r14, pt0
+
+ mtpr r1, pt1 // get a scratch reg
+ and r11, osfps_m_mode, r1 // get mode bit
+
+ bis r11, r31, r25 // save ps
+ beq r1, 1f // if zero we are in kern now
+
+ bis r31, r31, r25 // set the new ps
+ mtpr r30, pt_usp // save user stack
+
+ mfpr r30, pt_ksp // get kern stack
+1:
+ mfpr r14, exc_addr // get pc into r14 in case stack writes fault
+
+ lda sp, 0-osfsf_c_size(sp) // allocate stack space
+ mtpr r31, ev5__ps // Set Ibox current mode to kernel
+
+ mfpr r1, pt_entArith
+ stq r14, osfsf_pc(sp) // save pc
+
+ stq r17, osfsf_a1(sp)
+ mfpr r17, ev5__exc_mask // Get exception register mask IPR - no mtpr exc_sum in next cycle
+
+ stq r29, osfsf_gp(sp)
+ stq r16, osfsf_a0(sp) // save regs
+
+ bis r13, r31, r16 // move exc_sum to r16
+ stq r18, osfsf_a2(sp)
+
+ stq r11, osfsf_ps(sp) // save ps
+ mfpr r29, pt_kgp // get the kern gp
+
+ mfpr r14, pt0 // restore logout frame pointer from pt0
+ bis r25, r31, r11 // set new ps
+
+ mtpr r1, pt10 // Set new PC
+ mfpr r1, pt1
+
+// XXX bugnion pvc$jsr armc, bsr=1, dest=1
+ ret r31, (r12) // return if no outstanding arithmetic error
+
+
+
+// sys_enter_console - Common PALcode for ENTERING console
+//
+// Entry:
+// Entered when PAL wants to enter the console.
+// usually as the result of a HALT instruction or button,
+// or catastrophic error.
+//
+// Regs on entry...
+//
+// R0 = halt code
+// pt0 <- r0
+//
+// Function:
+//
+// Save all readable machine state, and "call" the console
+//
+// Returns:
+//
+//
+// Notes:
+//
+// In these routines, once the save state routine has been executed,
+// the remainder of the registers become scratchable, as the only
+// "valid" copy of them is the "saved" copy.
+//
+// Any registers or PTs that are modified before calling the save
+// routine will have there data lost. The code below will save all
+// state, but will loose pt 0,4,5.
+//
+//
+
+ ALIGN_BLOCK
+EXPORT(sys_enter_console)
+ mtpr r1, pt4
+ mtpr r3, pt5
+ subq r31, 1, r1
+ sll r1, 42, r1
+ ldah r1, 1(r1)
+
+ /* taken from scrmax, seems like the obvious thing to do */
+ mtpr r1, exc_addr
+ mfpr r1, pt4
+ mfpr r3, pt5
+ STALL
+ STALL
+ hw_rei_stall
+
+
+//
+// sys_exit_console - Common PALcode for ENTERING console
+//
+// Entry:
+// Entered when console wants to reenter PAL.
+// usually as the result of a CONTINUE.
+//
+//
+// Regs' on entry...
+//
+//
+// Function:
+//
+// Restore all readable machine state, and return to user code.
+//
+//
+//
+//
+ ALIGN_BLOCK
+sys_exit_console:
+
+ GET_IMPURE(r1)
+
+ // clear lock and intr_flags prior to leaving console
+ rc r31 // clear intr_flag
+ // lock flag cleared by restore_state
+ // TB's have been flushed
+
+ ldq_p r3, (cns_gpr+(8*3))(r1) // restore r3
+ ldq_p r1, (cns_gpr+8)(r1) // restore r1
+ hw_rei_stall // back to user
+
+
+// kludge_initial_pcbb - PCB for Boot use only
+
+ ALIGN_128
+.globl kludge_initial_pcbb
+kludge_initial_pcbb: // PCB is 128 bytes long
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+ nop
+ nop
+ nop
+ nop
+
+
+// SET_SC_BC_CTL subroutine
+//
+// Subroutine to set the SC_CTL, BC_CONFIG, and BC_CTL registers and
+// flush the Scache
+// There must be no outstanding memory references -- istream or
+// dstream -- when these registers are written. EV5 prefetcher is
+// difficult to turn off. So, this routine needs to be exactly 32
+// instructions long// the final jmp must be in the last octaword of a
+// page (prefetcher doesn't go across page)
+//
+//
+// Register expecations:
+// r0 base address of CBOX iprs
+// r5 value to set sc_ctl to (flush bit is added in)
+// r6 value to set bc_ctl to
+// r7 value to set bc_config to
+// r10 return address
+// r19 old sc_ctl value
+// r20 old value of bc_ctl
+// r21 old value of bc_config
+// r23 flush scache flag
+// Register usage:
+// r17 sc_ctl with flush bit cleared
+// r22 loop address
+//
+//
+set_sc_bc_ctl:
+ ret r31, (r10) // return to where we came from
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