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-rw-r--r--tests/configs/inorder-timing.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index baeab677a..a92c61ba1 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -40,7 +40,8 @@ cpu.clock = '2GHz'
system = System(cpu = cpu,
physmem = SimpleDRAM(),
- membus = CoherentBus())
+ membus = CoherentBus(),
+ mem_mode = "timing")
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller