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-rw-r--r--tests/configs/inorder-timing.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index b19014328..30e12f777 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -42,6 +42,7 @@ system = System(cpu = cpu,
physmem = DDR3_1600_x64(),
membus = CoherentBus(),
mem_mode = "timing")
+system.clock = '1GHz'
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller