diff options
Diffstat (limited to 'tests/configs/memtest-filter.py')
| -rw-r--r-- | tests/configs/memtest-filter.py | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py index 35d64a793..42dd05639 100644 --- a/tests/configs/memtest-filter.py +++ b/tests/configs/memtest-filter.py @@ -36,8 +36,7 @@ nb_cores = 8 cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated -system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentXBar(), +system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentXBar(width=16, snoop_filter = SnoopFilter())) # Dummy voltage domain for all our clock domains @@ -63,15 +62,11 @@ for cpu in cpus: # All cpus are associated with cpu_clk_domain cpu.clk_domain = system.cpu_clk_domain cpu.l1c = L1Cache(size = '32kB', assoc = 4) - cpu.l1c.cpu_side = cpu.test + cpu.l1c.cpu_side = cpu.port cpu.l1c.mem_side = system.toL2Bus.slave - system.funcbus.slave = cpu.functional system.system_port = system.membus.slave -# connect reference memory to funcbus -system.funcmem.port = system.funcbus.master - # connect memory to membus system.physmem.port = system.membus.master @@ -82,6 +77,3 @@ system.physmem.port = system.membus.master root = Root( full_system = False, system = system ) root.system.mem_mode = 'timing' -#root.trace.flags="Cache CachePort MemoryAccess" -#root.trace.cycle=1 - |