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-rw-r--r--tests/configs/memtest-filter.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py
index 4de009d76..35d64a793 100644
--- a/tests/configs/memtest-filter.py
+++ b/tests/configs/memtest-filter.py
@@ -37,9 +37,9 @@ cpus = [ MemTest() for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
- funcbus = NoncoherentBus(),
+ funcbus = NoncoherentXBar(),
physmem = SimpleMemory(),
- membus = CoherentBus(width=16, snoop_filter = SnoopFilter()))
+ membus = CoherentXBar(width=16, snoop_filter = SnoopFilter()))
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain()
system.clk_domain = SrcClockDomain(clock = '1GHz',
@@ -50,8 +50,8 @@ system.clk_domain = SrcClockDomain(clock = '1GHz',
system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
voltage_domain = system.voltage_domain)
-system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16,
- snoop_filter = SnoopFilter())
+system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16,
+ snoop_filter = SnoopFilter())
system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master