diff options
Diffstat (limited to 'tests/configs/memtest-ruby.py')
| -rw-r--r-- | tests/configs/memtest-ruby.py | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index a0500458a..004ff644a 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -80,12 +80,16 @@ options.num_cpus = nb_cores system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), physmem = SimpleMemory(null = True), - funcbus = NoncoherentBus(), - clk_domain = SrcClockDomain(clock = options.sys_clock)) + funcbus = NoncoherentBus()) +# Dummy voltage domain for all our clock domains +system.voltage_domain = VoltageDomain() +system.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = system.voltage_domain) # Create a seperate clock domain for components that should run at # CPUs frequency -system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') +system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', + voltage_domain = system.voltage_domain) # All cpus are associated with cpu_clk_domain for cpu in cpus: @@ -96,7 +100,8 @@ system.mem_ranges = AddrRange('256MB') Ruby.create_system(options, system) # Create a separate clock domain for Ruby -system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) assert(len(cpus) == len(system.ruby._cpu_ruby_ports)) |