diff options
Diffstat (limited to 'tests/configs/memtest.py')
| -rw-r--r-- | tests/configs/memtest.py | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index f56edef4a..6fe244acf 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 10 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 @@ -57,7 +57,8 @@ cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = PhysicalMemory(), - physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16)) + physmem = PhysicalMemory(), + membus = Bus(clock="500GHz", width=16)) # l2cache & bus system.toL2Bus = Bus(clock="500GHz", width=16) @@ -67,18 +68,12 @@ system.l2c.cpu_side = system.toL2Bus.port # connect l2c to membus system.l2c.mem_side = system.membus.port -which_port = 0 # add L1 caches for cpu in cpus: cpu.l1c = L1(size = '32kB', assoc = 4) cpu.l1c.cpu_side = cpu.test cpu.l1c.mem_side = system.toL2Bus.port - if which_port == 0: - system.funcmem.port = cpu.functional - which_port = 1 - else: - system.funcmem.functional = cpu.functional - + system.funcmem.port = cpu.functional # connect memory to membus system.physmem.port = system.membus.port |