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-rw-r--r--tests/configs/memtest.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 66e49a63e..c1358eecd 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -86,7 +86,7 @@ system.physmem.port = system.membus.port
# run simulation
# -----------------------
-root = Root( system = system )
+root = Root( full_system = False, system = system )
root.system.mem_mode = 'timing'
#root.trace.flags="Cache CachePort MemoryAccess"
#root.trace.cycle=1