diff options
Diffstat (limited to 'tests/configs/memtest.py')
| -rw-r--r-- | tests/configs/memtest.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index fbd18b779..e1bdc64fa 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -37,9 +37,9 @@ cpus = [ MemTest() for i in xrange(nb_cores) ] # system simulated system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False), - funcbus = NoncoherentBus(), + funcbus = NoncoherentXBar(), physmem = SimpleMemory(), - membus = CoherentBus(width=16)) + membus = CoherentXBar(width=16)) # Dummy voltage domain for all our clock domains system.voltage_domain = VoltageDomain() system.clk_domain = SrcClockDomain(clock = '1GHz', @@ -50,7 +50,7 @@ system.clk_domain = SrcClockDomain(clock = '1GHz', system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', voltage_domain = system.voltage_domain) -system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16) +system.toL2Bus = CoherentXBar(clk_domain = system.cpu_clk_domain, width=16) system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master |