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-rw-r--r--tests/configs/o3-timing-mp.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 331e2c569..1e414294c 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -73,6 +73,7 @@ for cpu in cpus:
L1(size = '32kB', assoc = 4))
# connect cpu level-1 caches to shared level-2 cache
cpu.connectMemPorts(system.toL2Bus)
+ cpu.clock = '2GHz'
# connect memory to membus
system.physmem.port = system.membus.port