summaryrefslogtreecommitdiff
path: root/tests/configs/o3-timing-mp.py
diff options
context:
space:
mode:
Diffstat (limited to 'tests/configs/o3-timing-mp.py')
-rw-r--r--tests/configs/o3-timing-mp.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 95323c2f6..1974d686f 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -62,10 +62,10 @@ Bus())
# l2cache & bus
system.toL2Bus = Bus()
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
+system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
-system.l2c.mem_side = system.membus.port
+system.l2c.mem_side = system.membus.slave
# add L1 caches
for cpu in cpus:
@@ -76,10 +76,10 @@ for cpu in cpus:
cpu.clock = '2GHz'
# connect memory to membus
-system.physmem.port = system.membus.port
+system.physmem.port = system.membus.master
# connect system port to membus
-system.system_port = system.membus.port
+system.system_port = system.membus.slave
# -----------------------
# run simulation