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-rw-r--r--tests/configs/o3-timing.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index c573277d1..050e4050e 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -48,8 +48,8 @@ from common.O3_ARM_v7a import O3_ARM_v7a_3
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv['TARGET_ISA'] == "arm":
- root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+ root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=O3_ARM_v7a_3).create_root()
else:
- root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+ root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
cpu_class=DerivO3CPU).create_root()