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-rw-r--r--tests/configs/o3-timing.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 732cd2d43..a10079ab8 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -49,7 +49,7 @@ cpu.clock = '2GHz'
system = System(cpu = cpu,
physmem = SimpleMemory(),
- membus = Bus())
+ membus = CoherentBus())
system.system_port = system.membus.slave
system.physmem.port = system.membus.master
# create the interrupt controller