summaryrefslogtreecommitdiff
path: root/tests/configs/pc-o3-timing.py
diff options
context:
space:
mode:
Diffstat (limited to 'tests/configs/pc-o3-timing.py')
-rw-r--r--tests/configs/pc-o3-timing.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index c4317ec23..6bab4c448 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8),
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8),
PageTableWalkerCache(),
PageTableWalkerCache())
# create the interrupt controller