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-rw-r--r--tests/configs/pc-o3-timing.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index f3b8e700f..a04b04134 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -87,8 +87,8 @@ mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.iocache = IOCache(addr_range=mem_size)
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
system.cpu = cpu
#create the l1/l2 bus
@@ -96,8 +96,8 @@ system.toL2Bus = Bus()
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),