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-rw-r--r--tests/configs/pc-o3-timing.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index 0b8b9381f..2d3019daf 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -92,7 +92,7 @@ system.iocache.mem_side = system.membus.slave
system.cpu = cpu
#create the l1/l2 bus
-system.toL2Bus = Bus()
+system.toL2Bus = CoherentBus()
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)