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-rw-r--r--tests/configs/pc-simple-atomic.py6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index 44ba51b3c..74d47fe41 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -50,9 +50,9 @@ system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
-cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
- L1(size = '32kB', assoc = 4),
- L2(size = '4MB', assoc = 8),
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
+ L1Cache(size = '32kB', assoc = 4),
+ L2Cache(size = '4MB', assoc = 8),
PageTableWalkerCache(),
PageTableWalkerCache())
# create the interrupt controller