summaryrefslogtreecommitdiff
path: root/tests/configs/pc-simple-timing-ruby.py
diff options
context:
space:
mode:
Diffstat (limited to 'tests/configs/pc-simple-timing-ruby.py')
-rw-r--r--tests/configs/pc-simple-timing-ruby.py3
1 files changed, 3 insertions, 0 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 0753472bc..23a0bb3d0 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -74,5 +74,8 @@ for (i, cpu) in enumerate(system.cpu):
cpu.interrupts.int_slave = system.piobus.master
cpu.clock = '2GHz'
+ # Set access_phys_mem to True for ruby port
+ system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+
root = Root(full_system = True, system = system)
m5.ticks.setGlobalFrequency('1THz')