diff options
Diffstat (limited to 'tests/configs/pc-simple-timing-ruby.py')
| -rw-r--r-- | tests/configs/pc-simple-timing-ruby.py | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py index 7fd9c0b5f..fcbfd6b7f 100644 --- a/tests/configs/pc-simple-timing-ruby.py +++ b/tests/configs/pc-simple-timing-ruby.py @@ -57,17 +57,22 @@ options.num_cpus = 2 mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('timing', options.num_cpus, mdesc=mdesc, Ruby=True) +# Dummy voltage domain for all our clock domains +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') -system.clk_domain = SrcClockDomain(clock = '1GHz') -system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') +system.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = system.voltage_domain) +system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', + voltage_domain = system.voltage_domain) system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) for i in xrange(options.num_cpus)] Ruby.create_system(options, system, system.piobus, system._dma_ports) # Create a seperate clock domain for Ruby -system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) for (i, cpu) in enumerate(system.cpu): # create the interrupt controller |