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-rw-r--r--tests/configs/pc-simple-timing-ruby.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/configs/pc-simple-timing-ruby.py b/tests/configs/pc-simple-timing-ruby.py
index 19c38dc32..18c990930 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -63,7 +63,7 @@ system.clk_domain = SrcClockDomain(clock = '1GHz',
system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
voltage_domain = system.voltage_domain)
system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
- for i in xrange(options.num_cpus)]
+ for i in range(options.num_cpus)]
Ruby.create_system(options, True, system, system.iobus, system._dma_ports)