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Diffstat (limited to 'tests/configs/pc-simple-timing.py')
| -rw-r--r-- | tests/configs/pc-simple-timing.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index 97a607d8e..b5117f2fe 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -106,6 +106,8 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4), PageTableWalkerCache(), PageTableWalkerCache()) +# create the interrupt controller +cpu.createInterruptController() # connect cpu level-1 caches to shared level-2 cache cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.clock = '2GHz' |