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-rw-r--r--tests/configs/pc-simple-timing.py18
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index 8a44300e5..bfbf926dc 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -40,8 +40,8 @@ mem_size = '128MB'
# ====================
class L1(BaseCache):
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
block_size = 64
mshrs = 4
tgts_per_mshr = 8
@@ -53,8 +53,8 @@ class L1(BaseCache):
class L2(BaseCache):
block_size = 64
- hit_latency = '10ns'
- response_latency = '10ns'
+ hit_latency = 20
+ response_latency = 20
mshrs = 92
tgts_per_mshr = 16
write_buffers = 8
@@ -65,8 +65,8 @@ class L2(BaseCache):
class PageTableWalkerCache(BaseCache):
assoc = 2
block_size = 64
- hit_latency = '1ns'
- response_latency = '1ns'
+ hit_latency = 2
+ response_latency = 2
mshrs = 10
size = '1kB'
tgts_per_mshr = 12
@@ -77,8 +77,8 @@ class PageTableWalkerCache(BaseCache):
class IOCache(BaseCache):
assoc = 8
block_size = 64
- hit_latency = '50ns'
- response_latency = '50ns'
+ hit_latency = 50
+ response_latency = 50
mshrs = 20
size = '1kB'
tgts_per_mshr = 12
@@ -95,7 +95,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
system.cpu = cpu
#create the iocache
-system.iocache = IOCache()
+system.iocache = IOCache(clock = '1GHz')
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave