1 files changed, 2 insertions, 52 deletions
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index bfbf926dc..990179008 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -31,60 +31,10 @@ from m5.objects import *
 m5.util.addToPath('../configs/common')
 from Benchmarks import SysConfig
 import FSConfig
-
+from Caches import *
 
 mem_size = '128MB'
 
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
-
-# ---------------------
-# Page table walker cache
-# ---------------------
-class PageTableWalkerCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    size = '1kB'
-    tgts_per_mshr = 12
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
-    assoc = 8
-    block_size = 64
-    hit_latency = 50
-    response_latency = 50
-    mshrs = 20
-    size = '1kB'
-    tgts_per_mshr = 12
-    addr_ranges = [AddrRange(0, size=mem_size)]
-    forward_snoops = False
-
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
 #the system
@@ -95,7 +45,7 @@ system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
 system.cpu = cpu
 
 #create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
 system.iocache.cpu_side = system.iobus.master
 system.iocache.mem_side = system.membus.slave