diff options
Diffstat (limited to 'tests/configs/pc-simple-timing.py')
| -rw-r--r-- | tests/configs/pc-simple-timing.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py index cbfda22a2..97a607d8e 100644 --- a/tests/configs/pc-simple-timing.py +++ b/tests/configs/pc-simple-timing.py @@ -92,14 +92,14 @@ system.cpu = cpu #create the l1/l2 bus system.toL2Bus = Bus() system.iocache = IOCache(addr_range=mem_size) -system.iocache.cpu_side = system.iobus.port -system.iocache.mem_side = system.membus.port +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave #connect up the l2 cache system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.port -system.l2c.mem_side = system.membus.port +system.l2c.cpu_side = system.toL2Bus.master +system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), |