diff options
Diffstat (limited to 'tests/configs/realview-simple-atomic.py')
| -rw-r--r-- | tests/configs/realview-simple-atomic.py | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py index b6a77e38e..55c5d2409 100644 --- a/tests/configs/realview-simple-atomic.py +++ b/tests/configs/realview-simple-atomic.py @@ -73,26 +73,23 @@ class IOCache(BaseCache): cpu = AtomicSimpleCPU(cpu_id=0) #the system system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False) -system.iocache = IOCache() -system.iocache.cpu_side = system.iobus.master -system.iocache.mem_side = system.membus.slave system.cpu = cpu -#create the l1/l2 bus -system.toL2Bus = CoherentBus() -#connect up the l2 cache -system.l2c = L2(size='4MB', assoc=8) -system.l2c.cpu_side = system.toL2Bus.master -system.l2c.mem_side = system.membus.slave +#create the iocache +system.iocache = IOCache() +system.iocache.cpu_side = system.iobus.master +system.iocache.mem_side = system.membus.slave -#connect up the cpu and l1s -cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) +#connect up the cpu and caches +cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4), + L2(size = '4MB', assoc = 8)) # create the interrupt controller cpu.createInterruptController() -# connect cpu level-1 caches to shared level-2 cache -cpu.connectAllPorts(system.toL2Bus, system.membus) +# connect cpu and caches to the rest of the system +cpu.connectAllPorts(system.membus) +# set the cpu clock along with the caches and l1-l2 bus cpu.clock = '2GHz' root = Root(full_system=True, system=system) |