diff options
Diffstat (limited to 'tests/configs/realview-simple-timing-dual.py')
| -rw-r--r-- | tests/configs/realview-simple-timing-dual.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py index 1c86f42bf..5b8e6e0e3 100644 --- a/tests/configs/realview-simple-timing-dual.py +++ b/tests/configs/realview-simple-timing-dual.py @@ -46,14 +46,14 @@ system.cpu = cpus system.toL2Bus = CoherentBus(clock = '2GHz') #connect up the l2 cache -system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) +system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.master system.l2c.mem_side = system.membus.slave #connect up the cpu and l1s for c in cpus: - c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), - L1(size = '32kB', assoc = 4)) + c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), + L1Cache(size = '32kB', assoc = 4)) # create the interrupt controller c.createInterruptController() # connect cpu level-1 caches to shared level-2 cache |