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-rw-r--r--tests/configs/realview-simple-timing.py8
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 8d1840571..1e27a5dc9 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -76,14 +76,14 @@ system.cpu = cpu
#create the l1/l2 bus
system.toL2Bus = Bus()
system.iocache = IOCache()
-system.iocache.cpu_side = system.iobus.port
-system.iocache.mem_side = system.membus.port
+system.iocache.cpu_side = system.iobus.master
+system.iocache.mem_side = system.membus.slave
#connect up the l2 cache
system.l2c = L2(size='4MB', assoc=8)
-system.l2c.cpu_side = system.toL2Bus.port
-system.l2c.mem_side = system.membus.port
+system.l2c.cpu_side = system.toL2Bus.master
+system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),