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-rw-r--r--tests/configs/realview-simple-timing.py2
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 1e27a5dc9..a55358306 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -88,6 +88,8 @@ system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'