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-rw-r--r--tests/configs/realview-simple-timing.py42
1 files changed, 2 insertions, 40 deletions
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 28cd3163f..4bb641e80 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -30,45 +30,7 @@ import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
-
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
- hit_latency = 2
- response_latency = 2
- block_size = 64
- mshrs = 4
- tgts_per_mshr = 8
- is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
- block_size = 64
- hit_latency = 20
- response_latency = 20
- mshrs = 92
- tgts_per_mshr = 16
- write_buffers = 8
-
-# ---------------------
-# I/O Cache
-# ---------------------
-class IOCache(BaseCache):
- assoc = 8
- block_size = 64
- hit_latency = 50
- response_latency = 50
- mshrs = 20
- size = '1kB'
- tgts_per_mshr = 12
- addr_ranges = [AddrRange(0, size='256MB')]
- forward_snoops = False
+from Caches import *
#cpu
cpu = TimingSimpleCPU(cpu_id=0)
@@ -78,7 +40,7 @@ system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.cpu = cpu
#create the iocache
-system.iocache = IOCache(clock = '1GHz')
+system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave